From 68a835987f60866b6f3bb37733cd9f8035435084 Mon Sep 17 00:00:00 2001 From: Kaiser <706598421@qq.com> Date: Tue, 30 Dec 2025 15:21:11 +0800 Subject: [PATCH] TEST --- Core/Inc/FreeRTOSConfig.h | 153 ++++++ Core/Src/APPDEF.H | 80 +++ Core/Src/StepMotor.c | 659 ++++++++++++++++++++++ Core/Src/TIM.c | 151 +++++ Core/Src/freertos.c | 59 ++ Core/Src/main.c | 532 ++++++++++++++++++ Core/Src/stm32f1xx_hal_msp.c | 293 ++++++++++ Core/Src/stm32f1xx_hal_timebase_tim.c | 129 +++++ Core/Src/stm32f1xx_it.c | 245 +++++++++ Core/Src/system_stm32f1xx.c | 406 ++++++++++++++ MDK-ARM/YouSuan.uvoptx | 765 ++++++++++++++++++++++++++ MDK-ARM/YouSuan.uvprojx | 660 ++++++++++++++++++++++ 12 files changed, 4132 insertions(+) create mode 100644 Core/Inc/FreeRTOSConfig.h create mode 100644 Core/Src/APPDEF.H create mode 100644 Core/Src/StepMotor.c create mode 100644 Core/Src/TIM.c create mode 100644 Core/Src/freertos.c create mode 100644 Core/Src/main.c create mode 100644 Core/Src/stm32f1xx_hal_msp.c create mode 100644 Core/Src/stm32f1xx_hal_timebase_tim.c create mode 100644 Core/Src/stm32f1xx_it.c create mode 100644 Core/Src/system_stm32f1xx.c create mode 100644 MDK-ARM/YouSuan.uvoptx create mode 100644 MDK-ARM/YouSuan.uvprojx diff --git a/Core/Inc/FreeRTOSConfig.h b/Core/Inc/FreeRTOSConfig.h new file mode 100644 index 0000000..10f8503 --- /dev/null +++ b/Core/Inc/FreeRTOSConfig.h @@ -0,0 +1,153 @@ +/* USER CODE BEGIN Header */ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ +/* USER CODE END Header */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * These parameters and more are described within the 'configuration' section of the + * FreeRTOS API documentation available on the FreeRTOS.org web site. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* USER CODE BEGIN Includes */ +/* Section where include file can be added */ +/* USER CODE END Includes */ + +/* Ensure definitions are only used by the compiler, and not by the assembler. */ +#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) + #include + extern uint32_t SystemCoreClock; +#endif +#ifndef CMSIS_device_header +#define CMSIS_device_header "stm32f1xx.h" +#endif /* CMSIS_device_header */ + +#define configUSE_PREEMPTION 1 +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( SystemCoreClock ) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES ( 56 ) +#define configMINIMAL_STACK_SIZE ((uint16_t)128) +#define configTOTAL_HEAP_SIZE ((size_t)5120) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 2 ) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH 256 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xQueueGetMutexHolder 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_eTaskGetState 1 + +/* + * The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used + * by the application thus the correct define need to be enabled below + */ +#define USE_FreeRTOS_HEAP_4 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 4 +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +/* USER CODE BEGIN 1 */ +#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} +/* USER CODE END 1 */ + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler + +/* IMPORTANT: After 10.3.1 update, Systick_Handler comes from NVIC (if SYS timebase = systick), otherwise from cmsis_os2.c */ + +#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0 + +/* USER CODE BEGIN Defines */ +/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */ +/* USER CODE END Defines */ + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Core/Src/APPDEF.H b/Core/Src/APPDEF.H new file mode 100644 index 0000000..546cc35 --- /dev/null +++ b/Core/Src/APPDEF.H @@ -0,0 +1,80 @@ +#include +#include "stdbool.h" +#include "cmsis_os.h" +//extern void delay_us(uint32_t us); +#include "stdlib.h" +#include "math.h" +//#include "MBM.H" +extern void MAX6675_Init(void); +extern void BIOS_GPIO_Init( void ); +extern void BIOS_TIM8_Init( void ); +extern void BIOS_TIM5_Init( void ); +extern void USARTHMIInit( void ); + +extern void TIM4_CH1_CTRL(uint16_t ARRValue, uint16_t CCRValue ); +extern void TIM4_CH1_CMD( _Bool CMD ); +extern void TIM4_CH1_DIR( _Bool CMD ); +extern void TIM4_IECMD( _Bool CMD ); +extern void TIM3_CH2_CTRL(uint16_t ARRValue, uint16_t CCRValue ); +extern void TIM3_CH2_CMD( _Bool CMD ); +extern void TIM3_CH2_DIR( _Bool CMD ); +extern void TIM3_IECMD( _Bool CMD ); + + + +enum enumPumpSelect +{ + M1 = 0, + M2, + M3, + M4, + M5, + M6, + M7, + pumpMax + +}; +extern enum enumPumpSelect PumpSelect[pumpMax]; +extern volatile uint32_t PluseCount[7u]; // +extern int32_t CoordinateSet[pumpMax]; // Ä¿±êλÖà +extern void SolidValve_H2SO4( uint8_t channel, _Bool state ); +extern void AirValve_Pump(_Bool state); +extern void StandardValve_Pump( _Bool state); + +extern void MotorCTRLInitiate( void ); + +extern float Temperature[6]; +#include "stdio.h" +#include "string.h" +#include "math.h" +extern void DataPrint(uint8_t *buf, uint8_t len); +extern osSemaphoreId semDataBack; +extern uint8_t DataInbuf[60u]; + +struct Pset { + uint16_t CRC_Head; // CRCУÑéÍ· + + uint16_t PowerSet[6]; + uint16_t HeatTimeSet[6]; + uint16_t LimitTemp[6]; + int16_t PowerComp[6]; + uint16_t AirTimeOutSet; + uint16_t WashTimeOutSet; + uint16_t WeightSet[6]; + float WeightComp[6]; + float WeightSlopeSet[6]; + float H2SO4SlopeSet[6]; + uint16_t CRC_Tail; // CRCУÑéβ +}; + + +extern struct Pset Set; +extern void FM24Init(void); +extern void FM24_Write(uint16_t addr, uint8_t *data, uint8_t len); +extern void FM24_Read(uint16_t addr, uint8_t *data, uint8_t len); +#define RW_Set 0x0200u +#define CRCHead 0xAA55u +#define CRCEnd 0x5AA5u + + + diff --git a/Core/Src/StepMotor.c b/Core/Src/StepMotor.c new file mode 100644 index 0000000..05f89d7 --- /dev/null +++ b/Core/Src/StepMotor.c @@ -0,0 +1,659 @@ +#include "APPDEF.H" + + +enum enumPumpSelect PumpSelect[pumpMax]; +/******************************** ¹¦ÄÜ˵Ã÷ ************************************* +* +*******************************************************************************/ +void Motor_IECMD( enum enumPumpSelect Select, _Bool CMD ) +{ + switch( Select ) + { + case M1: + TIM4_IECMD( CMD ); + break; + case M2: + TIM3_IECMD( CMD ); + break; + default: + break; + } + +} + +/********************************** ¹¦ÄÜ˵Ã÷ ************************************* +* »úе±ÛÔËÐÐËÙ¶ÈÉèÖà +*********************************************************************************/ +/********************************** ¹¦ÄÜ˵Ã÷ ************************************* +* »úе±ÛÔËÐÐËÙ¶ÈÉèÖà +*********************************************************************************/ +void Motor_PWM( enum enumPumpSelect Select, uint16_t Value ) +{ + switch( Select ) + { + case M1: + TIM4_CH1_CTRL( Value, Value / 2 ); + break; + case M2: + TIM3_CH2_CTRL( Value, Value / 2 ); + break; + default: + break; + } +} + +/********************************** ¹¦ÄÜ˵Ã÷ ************************************* +* »úе±ÛPWM¿ª¹Ø +*********************************************************************************/ +void Motor_PWMCmd( enum enumPumpSelect Select, _Bool State ) +{ + switch( Select ) + { + case M1: + TIM4_CH1_CMD( State ); + break; + case M2: + TIM3_CH2_CMD( State ); + break; + default: + break; + } +} +/********************************** ¹¦ÄÜ˵Ã÷ ************************************* +* »úе±ÛÔËÐз½ÏòÉèÖà +*********************************************************************************/ +void Motor_Dir( enum enumPumpSelect Select, _Bool State ) +{ + + switch( Select ) + { + case M1: +// TIM4_CH1_DIR( State); + break; + default: + break; + } +} +/********************************** ¹¦ÄÜ˵Ã÷ ************************************* +* »úе±Û¿ØÖÆÆ÷ʹÄÜ +*********************************************************************************/ +void Motor_En( enum enumPumpSelect Select, _Bool State ) +{ + switch( Select ) + { + case M1: + break; + default: + break; + } +} + +/******************************** ¹¦ÄÜ˵Ã÷ ************************************* +* TIMx Öжϴ¦Àíº¯Êý +*******************************************************************************/ + volatile uint32_t SetPluseCount[7u]; // ÉèÖÃÔËÐÐÂö³åÊý + volatile uint32_t PluseCount[7u]; // ʵ¼ÊÔËÐÐÂö³åÊý + volatile _Bool CountOver[7u] = {false}; // ¼ÆÊýÆ÷Òç³ö±êÖ¾ + volatile uint32_t SamplePumpSetPluseCount[7u]; // ÉèÖÃÔËÐÐÂö³åÊý + volatile uint32_t SamplePumpPluseCount[7u]; // ʵ¼ÊÔËÐÐÂö³åÊý + volatile _Bool SamplePumpCountOver[7u] = {false}; // ¼ÆÊýÆ÷Òç³ö±êÖ¾ + + +/********************************** ¹¦ÄÜ˵Ã÷ ************************************* +* »úе±ÛÔËÐÐÈÎÎñ +*********************************************************************************/ + +const uint32_t FullCoordinate[pumpMax] = { 20500u, 65000u,65000u }; +int32_t CoordinateSet[pumpMax]; // Ä¿±êλÖà +int32_t CoordinatePosition[pumpMax]; // ʵʱ¸üÐÂʵʱλÖà +uint32_t Position[pumpMax]; // ±¾´ÎÔËÐÐÆðʼλÖà +_Bool TaskisRunning[pumpMax] = {0}; // ·ÀÖ¹ÖØÈë±êÖ¾ +_Bool IdelEn[pumpMax] = { false,false,false}; // µç»ú¿ÕÏÐʹÄÜ +int32_t DCMotorSpeed[pumpMax]; // Ö±Á÷µç»úËÙ¶È + +uint32_t CoordinateSetOld[pumpMax]; // ÉÏ´ÎËùÔÚλÖà +int32_t Differ[pumpMax]; // ±¾´ÎËùÐèÔËÐÐÂö³åÊý +float SpeedSet[pumpMax]={ 100.0f, 1000.0f, 5000.0f }; // ×î¸ßËÙ¶Èp/s +uint32_t period[pumpMax] = { 20000u, 2000u, 2000u }; // PWMʵʱÖÜÆÚ +float Velocity[pumpMax] = { 0.0f, 20.0f, 20.0f }; // ʵʱËÙ¶È +uint32_t Shifting[pumpMax] = { 500u, 500u, 500u }; // ¼ÓËÙ¹ý³ÌÂö³åÊý +float Speeda[pumpMax] ={ 10000.0f, 10000.0f, 10000.0f }; // ¼ÓËÙ¶È p/(s*s) +float VelocityH[pumpMax]={ 10000.0f, 5000.0f, 5000.0f }; // ×î¸ßËÙ¶Èp/s +float VelocityL[pumpMax]={ 10.0f, 1000.0f, 1000.0f }; // ×îµÍËÙ¶Èp/s +float ShiftPluse[pumpMax]={ 100.0f, 1500.0f, 1500.0f }; // ±ê×¼×î´ó¼ÓËÙ¹ý³ÌÂö³åÊý +float VelocityMax[pumpMax] = { 10000.0f, 20.0f, 20.0f }; // ×î´óËÙ¶È +_Bool Direction[pumpMax] = { false,false,false}; // ÔËÐз½Ïò +/******************************** ¹¦ÄÜ˵Ã÷ ************************************* +* ËٶȼÓËÙ¶Èת»» +*******************************************************************************/ +static uint16_t SpeedOld[pumpMax]; +_Bool PumpShutDown[pumpMax] = {false, false}; // ¼±Í£±êÖ¾ +_Bool DirectionSet[pumpMax]; // Ä¿±ê·½Ïò +_Bool ENSet[pumpMax] = {false,false,false}; // ÊÇ·ñʹÄܵç»ú + +void SamplePumpSpeed_AcceleratedConver( enum enumPumpSelect Select, uint16_t Speed ) +{ + if( Speed != SpeedOld[Select] ) + { + Speeda[Select] = (Speed * Speed) / (2u * ShiftPluse[Select]); + SpeedOld[Select] = Speed; + } +} +/******************************** ¹¦ÄÜ˵Ã÷ ************************************* +* +*******************************************************************************/ + +_Bool SpeedMode[pumpMax]; +_Bool PositionMode[pumpMax]; +_Bool FindZero[pumpMax]; +_Bool FindedZero[pumpMax]; +void SamplePumpCtrl( enum enumPumpSelect Select ) +{ +// for(;;) + { + if((CoordinateSet[Select] != 0u) && (!TaskisRunning[Select])) + { + SamplePumpSpeed_AcceleratedConver(Select,SpeedSet[Select]); + + TaskisRunning[Select] = true; // ÖÃλ ·ÀÖØÈë±êÖ¾ + VelocityMax[Select] = 0; + period [Select] = 2000u; + Velocity[Select] = 6.0f; + Shifting[Select] = 100u; + + PluseCount[Select] = 0u; // ÇåÁã¼ÆÊýÂö³å + CountOver[Select] = false; // Çå³ý¼ÆÊýÆ÷Òç³ö + + SetPluseCount[Select] = CoordinateSet[Select]; // ÉèÖñÃÔËÐÐÂö³å + Motor_IECMD( Select, true); + Motor_Dir ( Select, DirectionSet[Select] ); // Ñ¡Ôñ·½Ïò + Motor_PWM ( Select, 100000.0f / VelocityL[Select] ); // ÖØÖÃpwmΪ×îµÍÊä³ö + osDelay( 50u ); + Motor_En ( Select, true ); // ²½½øµç»ú¿ØÖÆÆ÷¿ØÖÆʹÄÜ + + Shifting[Select] = SetPluseCount[Select] / 2u; + if( Shifting[Select] > ShiftPluse[Select] ) + Shifting[Select] = ShiftPluse[Select]; + Motor_PWMCmd( Select, true ); // ¿ªÆôÂö³åÊä³ö + + while( !CountOver[Select] ) // ¼ÆÊýÆ÷ûÓÐÒç³ö + { + if(PumpShutDown[Select]) + { + PumpShutDown[Select] = false; + break; + } + + if( PluseCount[Select] < Shifting[Select] ) // Ç°Shifting[Select]Âö³å¼ÓËÙ + { + Velocity[Select] = sqrt( 2* PluseCount[Select] * (Speeda[Select]/* / 2u*/)); + if( VelocityMax[Select] < Velocity[Select] ) + VelocityMax[Select] = Velocity[Select]; + if(Velocity[Select] > VelocityH[Select]) + Velocity[Select] = VelocityH[Select]; + if(Velocity[Select] < VelocityL[Select] ) + Velocity[Select] = VelocityL[Select]; + + if( Velocity[Select] > SpeedOld[Select]) + Velocity[Select] = SpeedOld[Select]; + period[Select] = 100000.0f / Velocity[Select]; + Motor_PWM( Select, period[Select] ); + } + else // ÖмäÔÈËÙ + if( PluseCount[Select] <= (SetPluseCount[Select] - Shifting[Select]) ) + { + period[Select] = 100000.0f / SpeedOld[Select]; + Motor_PWM( Select, period[Select] ); + while(CoordinateSet[Select] == 65535u) + { + PluseCount[Select] = 0; + osDelay( 5u ); + } + if(CoordinateSet[Select] == 0u) + { + SetPluseCount[Select] = Shifting[Select]*2; + PluseCount[Select] = Shifting[Select]+1; + } + } + else // ºóShifting[Select]Âö³å¼õËÙ + // if( PluseCount[Select] >= (SetPluseCount[Select] - Shifting[Select]) ) + { + + Velocity[Select] = sqrt( 2* (SetPluseCount[Select] - (float)PluseCount[Select]) * (Speeda[Select] / 2u)); + if(Velocity[Select] > VelocityH[Select]) + Velocity[Select] = VelocityH[Select]; + if(Velocity[Select] < VelocityL[Select] ) + Velocity[Select] = VelocityL[Select]; + period[Select] = 100000.0f / Velocity[Select]; + Motor_PWM( Select, period[Select] ); + } + osDelay( 5u ); + } +// usRegHoldingBuf[20u+Select*5u] = 0u; + osDelay( 15u ); + CoordinateSet[Select] = 0u; + Motor_En( Select, ENSet[Select] ); // ²½½øµç»ú¿ØÖÆÆ÷¿ØÖÆʹÄÜ + TaskisRunning[Select] = false; // Çå³ý·ÀÖØÈë±êÖ¾ + CountOver[Select] = false; // Çå³ý¼ÆÊýÆ÷Òç³ö + osDelay( 15u ); + } + else + { + osDelay(15); + } + } +} +static bool ArmInitIsRuning[pumpMax] = { false,false,false}; +/********************************** ¹¦ÄÜ˵Ã÷ ************************************* +* »úе±ÛÔËÐÐÈÎÎñ +*********************************************************************************/ +void ArmSoftCtrl( enum enumPumpSelect Select ) +{ + /*Vmin = 50p/s Vmax = 20000p/s At = 0.2s a = 100000p/s2 ¡÷s = 2000p ¡÷t = 0.001s P = 0.000001s */ + +//#define LowSpeed 40.0f +// for(;;) + { + + if( + (CoordinateSet[Select] != CoordinateSetOld[Select]) // Èç¹ûÄ¿±êλÖÃÓ뵱ǰλÖò»Í¬ + && !TaskisRunning[Select] // Èç¹û´ËÈÎÎñûÓÐÕýÔÚÔËÐÐ + &&!( ArmInitIsRuning[M3] // ÇÒËùÓеÄÈÎÎñûÓÐÕýÔÚ³õʼ»¯ + ) + ) + { + + TaskisRunning[Select] = true; // ÖÃλ ·ÀÖØÈë±êÖ¾ + + VelocityMax[Select] = 0; + + if( CoordinateSet[Select] > FullCoordinate[Select]) + { + /*usRegHoldingBuf[7] = */CoordinateSet[Select] = CoordinateSetOld[Select]; + osDelay(15); // ¼«ÏÞλÖñ£»¤ + } + + period [Select] = 20000u; //ÖÜÆÚ + Velocity[Select] = 500.0f; //ʵʱËÙ¶È + Shifting[Select] = 1500u; //¼ÓËÙÂö³å + + CoordinateSetOld[Select] = CoordinateSet[Select]; // + + PluseCount[Select] = 0u; // ÇåÁã¼ÆÊýÂö³å + CountOver[Select] = false; // Çå³ý¼ÆÊýÆ÷Òç³ö + + Differ[Select] = CoordinateSet[Select] - CoordinatePosition[Select]; // ¼ÆËãÉèÖÃλÖÃÓ뵱ǰλÖõÄÆ«²îºÍ·½Ïò + if(Differ[Select] != 0) + { + if( Differ[Select] > 0 ) + Direction[Select] = true; + if( Differ[Select] < 0 ) + Direction[Select] = false; + SetPluseCount[Select] = abs( Differ[Select]); // ÉèÖñÃÔËÐÐÂö³å + Position[Select] = CoordinatePosition[Select]; + + Motor_IECMD( Select, true); + Motor_Dir ( Select, ( Differ[Select] >= 0 ) ? false : true ); // Ñ¡Ôñ·½Ïò + Motor_PWM ( Select, period[Select] ); // ÖØÖÃpwmΪ×îµÍÊä³ö + osDelay( 50u ); + + Shifting[Select] = abs(Differ[Select]) / 2u; + if( Shifting[Select] > ShiftPluse[Select] ) + Shifting[Select] = ShiftPluse[Select]; + Motor_PWMCmd( Select, true ); // ¿ªÆôÂö³åÊä³ö + Motor_En ( Select, true ); // ²½½øµç»ú¿ØÖÆÆ÷¿ØÖÆʹÄÜ + while( !CountOver[Select] ) // ¼ÆÊýÆ÷ûÓÐÒç³ö + { + + // Ç°Shifting[Select]Âö³å¼ÓËÙÖÁÔÈËÙ²¢ÔÈËÙÔËÐÐ + if( PluseCount[Select] <= (abs(Differ[Select]) - Shifting[Select]) ) + { + + + if( Velocity[Select] < SpeedOld[Select]) + { + Velocity[Select] = sqrt( 2* PluseCount[Select] * (Speeda[Select] / 2u)); + if( Velocity[Select] > SpeedOld[Select]) + Velocity[Select] = SpeedOld[Select]; + + if( VelocityMax[Select] < Velocity[Select] ) + VelocityMax[Select] = Velocity[Select]; + if(Velocity[Select] > VelocityH[Select]) + Velocity[Select] = VelocityH[Select]; + if(Velocity[Select] < VelocityL[Select] ) + Velocity[Select] = VelocityL[Select]; + period[Select] = 1000000.0f / Velocity[Select]; + Motor_PWM( Select, period[Select] ); + } + + } + else//if( PluseCount[Select] >= (abs(Differ) - Shifting[Select]) ) // ºóShifting[Select]Âö³å¼õËÙ + { + + Velocity[Select] = sqrt( 2* (abs(Differ[Select]) - (float)PluseCount[Select]) * (Speeda[Select] / 2u)); + if( VelocityMax[Select] < Velocity[Select] ) + VelocityMax[Select] = Velocity[Select]; + if(Velocity[Select] > VelocityH[Select]) + Velocity[Select] = VelocityH[Select]; + if(Velocity[Select] < VelocityL[Select] ) + Velocity[Select] = VelocityL[Select]; + period[Select] = 1000000.0f / Velocity[Select]; + Motor_PWM( Select, period[Select] ); + } + osDelay( 1u ); + + if( Differ[Select] >= 0 ) // ¸ù¾Ý·½ÏòÆ«²îÀ´¼ÆË㵱ǰλÖà + { + CoordinatePosition[Select] = Position[Select] + PluseCount[Select]; + } + else + { + CoordinatePosition[Select] = Position[Select] - PluseCount[Select]; + } + + } + + if( Differ[Select] >= 0 ) // ¸ù¾Ý×îÖÕ¼ÆÊýÀ´¼ÆËã×îÖÕλÖà + { + CoordinatePosition[Select] = Position[Select] + PluseCount[Select]; + } + else + { + CoordinatePosition[Select] = Position[Select] - PluseCount[Select]; + } + } + Velocity[Select] = 0; + TaskisRunning[Select] = false; // Çå³ý·ÀÖØÈë±êÖ¾ + CountOver[Select] = false; // Çå³ý¼ÆÊýÆ÷Òç³ö + osDelay( 5u ); + } + else + { + osDelay(15); + } + } +} + + +//_Bool SpeedMode[pumpMax]; +//_Bool PositionMode[pumpMax]; + +void MotorCtrl(enum enumPumpSelect Select) +{ +// static _Bool SpeedModeOld[pumpMax]; +// static _Bool PositionModeOld[pumpMax]; + for(;;) + { + +// if( SpeedModeOld[Select] != SpeedMode[Select]) +// { +// SpeedModeOld[Select] = SpeedMode[Select]; +// Motor_IECMD( Select, SpeedModeOld[Select]); +// } +// if( PositionModeOld[Select] != PositionMode[Select]) +// { +// PositionModeOld[Select] = PositionMode[Select]; +// } +// if( PositionMode[Select] ) +// { +// SamplePumpCtrl(Select); +// } + + switch(Select) + { + case M1: + case M2: + SamplePumpCtrl(Select); + break; + case M3: + ArmSoftCtrl(Select); + break; + default: + break; + } + + + + + } + +} +#include "stm32f10x.h" + +/******************************** ¹¦ÄÜ˵Ã÷ ************************************* +* Öж϶˿ڳõʼ»¯Ê¹ÄÜ +*******************************************************************************/ +void BIOS_EXTI_Init( void ) +{ + +// // ¸¡¿ÕÊäÈëģʽ + + SET_BIT( RCC->APB2ENR, RCC_APB2ENR_IOPBEN ); + + GPIOB->BSRR |= 0x0002u; // ¶Ë¿ÚÊä³öΪ1£» +// GPIOF->BSRR |= 0x3800u; // ¶Ë¿ÚÊä³öΪ1£» +// GPIOE->BSRR |= 0x0040u; // ¶Ë¿ÚÊä³öΪ1£» +// SET_BIT( GPIOC->PUPDR, GPIO_PUPDR_PUPD0_0|GPIO_PUPDR_PUPD1_0|GPIO_PUPDR_PUPD2_0|GPIO_PUPDR_PUPD3_0 ); // IO¿ÚÅäÖà ÉÏÀ­ +// SET_BIT( GPIOF->PUPDR, GPIO_PUPDR_PUPD11_0|GPIO_PUPDR_PUPD12_0|GPIO_PUPDR_PUPD13_0 ); // IO¿ÚÅäÖà ÉÏÀ­ + CLEAR_BIT( GPIOB->CRL, GPIO_CRL_CNF1_0 ); + SET_BIT( GPIOB->CRL, GPIO_CRL_CNF1_1 ); + SET_BIT( GPIOB->ODR, GPIO_ODR_ODR1 ); // IO¿ÚÅäÖà ÉÏÀ­ +// MODIFY_REG( GPIOC->MODER, GPIO_MODER_MODE0, GPIO_MODER_MODE0_1 ); // IO¿ÚÅäÖà ¸´ÓÃÊä³ö +// MODIFY_REG( GPIOC->MODER, GPIO_MODER_MODE1, GPIO_MODER_MODE1_1 ); // IO¿ÚÅäÖà ¸´ÓÃÊä³ö +// MODIFY_REG( GPIOC->MODER, GPIO_MODER_MODE2, GPIO_MODER_MODE2_1 ); // IO¿ÚÅäÖà ¸´ÓÃÊä³ö +// MODIFY_REG( GPIOC->MODER, GPIO_MODER_MODE3, GPIO_MODER_MODE3_1 ); // IO¿ÚÅäÖà ¸´ÓÃÊä³ö +// MODIFY_REG( GPIOF->MODER, GPIO_MODER_MODE11, GPIO_MODER_MODE11_1 ); // IO¿ÚÅäÖà ¸´ÓÃÊä³ö +// MODIFY_REG( GPIOF->MODER, GPIO_MODER_MODE12, GPIO_MODER_MODE12_1 ); // IO¿ÚÅäÖà ¸´ÓÃÊä³ö +// MODIFY_REG( GPIOF->MODER, GPIO_MODER_MODE13, GPIO_MODER_MODE13_1 ); // IO¿ÚÅäÖà ¸´ÓÃÊä³ö + + +// SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); +// // ¿ªÆôÖжϸ´Óà +// SYSCFG->EXTICR[0] = +// SYSCFG_EXTICR1_EXTI1_PC +// |SYSCFG_EXTICR1_EXTI1_PC +// |SYSCFG_EXTICR1_EXTI2_PC +// |SYSCFG_EXTICR1_EXTI3_PC + ; +// SYSCFG->EXTICR[1] = +// SYSCFG_EXTICR2_EXTI6_PF; +// SYSCFG->EXTICR[2] = +// SYSCFG_EXTICR3_EXTI11_PF; +// SYSCFG->EXTICR[3] = +// SYSCFG_EXTICR4_EXTI12_PF +// |SYSCFG_EXTICR4_EXTI13_PF +// ; +SET_BIT( RCC->APB2ENR, RCC_APB2ENR_AFIOEN ); + + AFIO->EXTICR[0] = AFIO_EXTICR1_EXTI1_PB + // | AFIO_EXTICR1_EXTI1_PB +// | AFIO_EXTICR1_EXTI2_PA +// | AFIO_EXTICR1_EXTI3_PA +// ; +// AFIO->EXTICR[1] = AFIO_EXTICR2_EXTI4_PA +// | AFIO_EXTICR2_EXTI5_PA +// | AFIO_EXTICR2_EXTI6_PA +// | AFIO_EXTICR2_EXTI7_PA + ; + + + CLEAR_BIT( EXTI->IMR, 0xFFFFu ); // ½ûÖ¹ÖÐ¶Ï + + CLEAR_BIT( EXTI->EMR, 0xFFFFu ); // no event ÎÞÖжÏʼþ +// SET_BIT ( EXTI->RTSR, 0x0006u ); // rising edge trigger ÉÏÉýÑØ´¥·¢ + SET_BIT ( EXTI->FTSR, 0x0002u ); // falling edge trigger ϽµÑØ´¥·¢ + WRITE_REG( EXTI->PR, 0xFFFFu ); // ͨ¹ýд1Äܸ´Î»´¥·¢µÄÖжϱêÖ¾ + +// SET_BIT ( EXTI->IMR, 0x384Fu ); // ÔÊÐíÖÐ¶Ï +// // IOÖÐ¶Ï +// NVIC_EnableIRQ( EXTI0_IRQn ); + NVIC_EnableIRQ( EXTI1_IRQn ); +// NVIC_EnableIRQ( EXTI2_IRQn ); +// NVIC_EnableIRQ( EXTI3_IRQn ); +// NVIC_EnableIRQ( EXTI9_5_IRQn ); +// NVIC_EnableIRQ( EXTI15_10_IRQn ); + +} + +/********************************** ¹¦ÄÜ˵Ã÷ *********************************** +* ÖжϿª¹Ø¿ØÖÆ +*******************************************************************************/ +void EXTIx_IRQ_Enable( uint8_t EXTIx ) +{ + SET_BIT( EXTI->PR, 0x01u << EXTIx ); // д1¸´Î»Öжϱê־λ + SET_BIT( EXTI->IMR, 0x01u << EXTIx ); // ÔÊÐíÖжϡ£ +} + +void EXTIx_IRQ_Disable( uint8_t EXTIx ) +{ + CLEAR_BIT( EXTI->IMR, 0x01u << EXTIx ); // ½ûÖ¹ÖÐ¶Ï + SET_BIT( EXTI->PR, 0x01u << EXTIx ); // д1¸´Î»Öжϱê־λ +} + + + + + +uint16_t iz = 0; +void EXTI1_IRQHandler( void ) +{ + iz++; + SET_BIT( EXTI->PR, 0x01u << 1 ); // д1¸´Î»Öжϱê־λ + if(ArmInitIsRuning[M1] ) + { + if( !READ_BIT( GPIOB->IDR, GPIO_Pin_1 ) ) + { + EXTIx_IRQ_Disable( 1 ); + Motor_PWMCmd(M1, false ); + CoordinateSet[M1] = 0u; + CoordinatePosition[M1] = 0; + } + } + else + { + if( READ_BIT( GPIOB->IDR, GPIO_Pin_1 ) ) + { + EXTIx_IRQ_Disable( 1 ); + osDelay(400); + Motor_PWMCmd(M1, false ); + if(CoordinateSet[M1] >0) + CoordinatePosition[M1] = 1; + else + CoordinatePosition[M1] = -1; + + CoordinateSet[M1] = 0u; + } + } + +} + + +_Bool Exti_IOStateRead( enum enumPumpSelect Select ) +{ + _Bool state = false; + switch (Select) + { + case M1: + state = READ_BIT( GPIOB->IDR, GPIO_IDR_IDR1); + break; + default: + break; + } + return state; +} +void Exti_IRQ_Ctrl( enum enumPumpSelect Select, _Bool State ) +{ + switch (Select) + { + case M1: + State? EXTIx_IRQ_Enable(1) : EXTIx_IRQ_Disable(1); + break; + + default: + break; + } +} +void MotorZero_Init( enum enumPumpSelect Select) +{ + SET_BIT( GPIOA->BSRR, GPIO_BSRR_BS5 ); + FindedZero[Select] =false; + EXTIx_IRQ_Disable(0); + Motor_PWMCmd( Select, false ); + ArmInitIsRuning[Select] = true; + Exti_IRQ_Ctrl(Select, false); + Motor_En( Select, true ); + Motor_Dir( Select, true ); + osDelay(10u); + Motor_IECMD( Select, false ); + DCMotor_PWM( Select, 55 ); + if( !Exti_IOStateRead(Select) ) + { + Motor_Dir( Select, false ); + osDelay(10u); + Motor_PWMCmd( Select, true ); + osDelay(600u); + Motor_PWMCmd( Select, false ); + Motor_Dir( Select, true ); + osDelay(150u); + } + Exti_IRQ_Ctrl(Select, true); + Motor_PWMCmd( Select, true ); + CoordinateSet[Select] = 0u; + CoordinatePosition[Select] = 1u; + while( CoordinatePosition[Select] ) + { + PluseCount[Select] = 0u; + osDelay( 20u ); + } + PluseCount[Select] = 0u; + SetPluseCount[Select] = 0u; + CoordinateSet[Select] = 0u; + CoordinateSetOld[Select] = 0u; + Direction[Select] = false; + FindedZero[Select] =true; +// RegCoilsBufRst( (22u+Select*3u) ); + usRegHoldingBuf[43] = 0; + usRegInputBuf[43] = 2; + usRegHoldingBuf[7] = CoordinateSet[Select] = 0; + ArmInitIsRuning[Select] = FindZero[Select] = false; + SET_BIT( GPIOA->BSRR, GPIO_BSRR_BR5 ); +} + + + +BaseType_t temp1,temp2,temp3; +void _task_MotorCTRL( void * p_arg ) +{ + uint32_t arg = (uint32_t)p_arg; + MotorCtrl((enum enumPumpSelect)arg ); +} + +//osThreadDef( _task_MotorCTRL, osPriorityAboveNormal, 2u, 0u ); +osThreadId_t MName[pumpMax]; +TaskHandle_t xTaskHandles[pumpMax]; +void MotorCTRLInitiate( void ) +{ + SamplePumpSpeed_AcceleratedConver(M1,100); + SamplePumpSpeed_AcceleratedConver(M2,1000); + SamplePumpSpeed_AcceleratedConver(M3,100); + + temp1 = xTaskCreate(_task_MotorCTRL, // ÈÎÎñº¯Êý + "TaskName1", // ÈÎÎñÃû£¨ÓÃÓÚµ÷ÊÔ£© + 512, // ¶ÑÕ»´óС£¨ÒÔ¶ÑÕ»ÀàÐ͵ĴóСΪµ¥Î»£© + (void *)M1, // ´«µÝ¸øÈÎÎñµÄ²ÎÊý + osPriorityNormal, // ÈÎÎñÓÅÏȼ¶£¨¸ù¾ÝÐèÒªµ÷Õû£© + &xTaskHandles[M1]); // ÈÎÎñ¾ä±úµÄµØÖ·£¨ÓÃÓÚÒýÓã© + temp2 = xTaskCreate(_task_MotorCTRL, // ÈÎÎñº¯Êý + "TaskName2", // ÈÎÎñÃû£¨ÓÃÓÚµ÷ÊÔ£© + 512, // ¶ÑÕ»´óС£¨ÒÔ¶ÑÕ»ÀàÐ͵ĴóСΪµ¥Î»£© + (void *)M2, // ´«µÝ¸øÈÎÎñµÄ²ÎÊý + osPriorityNormal, // ÈÎÎñÓÅÏȼ¶£¨¸ù¾ÝÐèÒªµ÷Õû£© + &xTaskHandles[M2]); // ÈÎÎñ¾ä±úµÄµØÖ·£¨ÓÃÓÚÒýÓã© + temp3 = xTaskCreate(_task_MotorCTRL, // ÈÎÎñº¯Êý + "TaskName3", // ÈÎÎñÃû£¨ÓÃÓÚµ÷ÊÔ£© + 512, // ¶ÑÕ»´óС£¨ÒÔ¶ÑÕ»ÀàÐ͵ĴóСΪµ¥Î»£© + (void *)M3, // ´«µÝ¸øÈÎÎñµÄ²ÎÊý + osPriorityNormal, // ÈÎÎñÓÅÏȼ¶£¨¸ù¾ÝÐèÒªµ÷Õû£© + &xTaskHandles[M3]); // ÈÎÎñ¾ä±úµÄµØÖ·£¨ÓÃÓÚÒýÓã© + +} diff --git a/Core/Src/TIM.c b/Core/Src/TIM.c new file mode 100644 index 0000000..bf56f14 --- /dev/null +++ b/Core/Src/TIM.c @@ -0,0 +1,151 @@ + +#include "stdbool.h" +#include "stm32f10x.h" +#include "cmsis_os.h" + +///******************************** ¹¦ÄÜ˵Ã÷ ************************************* +//* TIM4 +//*******************************************************************************/ +//void BIOS_TIM4_Init( void ) +//{ +// SET_BIT( RCC->APB2ENR, RCC_APB2ENR_IOPDEN ); +// MODIFY_REG( GPIOD->CRH, 0x0FF00000u, 0x0B300000u ); // IO¿ÚÅäÖà PWM_OUT +// GPIO_PinRemapConfig(GPIO_Remap_TIM4, ENABLE); +// SET_BIT( RCC->APB1ENR, RCC_APB1ENR_TIM4EN ); // ´ò¿ªÊ±ÖÓ +// SET_BIT( RCC->APB1ENR, RCC_APB2ENR_AFIOEN ); // ´ò¿ª¸´ÓÃʱÖÓ +// SET_BIT( TIM4->EGR, TIM_EGR_UG ); // ³õʼ»¯ËùÓмĴæÆ÷ +// TIM4->CR1 = TIM_CR1_ARPE| TIM_CR1_URS; // ×Ô¶¯×°ÔØ Òç³öÖÐ¶Ï +// TIM4->PSC = SystemCoreClock / 1000000u - 1u; // ÉèÖÃÔ¤·ÖƵֵ +// TIM4->ARR = 100u - 1; // ÉèÖÃԤװÔØÖµ +// TIM4->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3PE; // ÉèÖüÆÊý¼«ÐԺ͹¤×÷ģʽ +//// TIM4->CCER = TIM_CCER_CC3E; // ʹÄÜͨµÀ + +// TIM4->CCR3 = 100/2u; // ÉèÖ÷­×ªÖµ +// NVIC_EnableIRQ(TIM4_IRQn); +// SET_BIT( TIM4->CR1, TIM_CR1_CEN ); // ʹÄܼÆÊýÆ÷ +//} +/******************************** ¹¦ÄÜ˵Ã÷ ************************************* +* TIM4->CH3 ¿ØÖÆ +*******************************************************************************/ + +void TIM4_CH1_CTRL(uint16_t ARRValue, uint16_t CCRValue ) +{ + TIM4->ARR = ARRValue; // ÉèÖÃԤװÔØ + TIM4->CCR1 = CCRValue; // ÉèÖ÷­×ªÖµ +} + +/******************************** ¹¦ÄÜ˵Ã÷ ************************************* +* TIM4->CH3 PWM¿ª¹Ø +*******************************************************************************/ + +void TIM4_CH1_CMD( _Bool CMD ) +{ + if( CMD ) + { + SET_BIT( TIM4->CR1,TIM_CR1_CEN ); + SET_BIT( TIM4->CCER,TIM_CCER_CC1E ); + } + else + { + CLEAR_BIT( TIM4->CCER,TIM_CCER_CC1E ); + CLEAR_BIT( TIM4->CR1,TIM_CR1_CEN ); + } +} +/******************************** ¹¦ÄÜ˵Ã÷ ************************************* +* DIR +*******************************************************************************/ + +//void TIM4_CH1_DIR( _Bool CMD ) +//{ +// if( CMD ) +// { +// GPIO_SetBits( GPIOD, GPIO_ODR_ODR13 ); +// } +// else +// { +// GPIO_ResetBits( GPIOD, GPIO_ODR_ODR13 ); +// } +//} +/******************************** ¹¦ÄÜ˵Ã÷ ************************************* +* +*******************************************************************************/ +void TIM4_IECMD( _Bool CMD ) +{ + if( CMD ) + { + SET_BIT(TIM4->DIER, TIM_DIER_CC1IE); // ʹÄÜÖÐ¶Ï + CLEAR_BIT( TIM4->SR, TIM_SR_UIF | TIM_SR_CC1IF ); // Çå³ýÖжϱê¼Ç + + } + else + { + CLEAR_BIT(TIM4->DIER,TIM_DIER_CC1IE); // ʧÄÜÖÐ¶Ï + CLEAR_BIT( TIM4->SR, TIM_SR_UIF | TIM_SR_CC1IF ); // Çå³ýÖжϱê¼Ç + } +} + + + + + + + +/******************************** ¹¦ÄÜ˵Ã÷ ************************************* +* TIM3->CH2 ¿ØÖÆ +*******************************************************************************/ + +void TIM3_CH2_CTRL(uint16_t ARRValue, uint16_t CCRValue ) +{ + TIM3->ARR = ARRValue; // ÉèÖÃԤװÔØ + TIM3->CCR2 = CCRValue; // ÉèÖ÷­×ªÖµ +} + +/******************************** ¹¦ÄÜ˵Ã÷ ************************************* +* TIM4->CH3 PWM¿ª¹Ø +*******************************************************************************/ + +void TIM3_CH2_CMD( _Bool CMD ) +{ + if( CMD ) + { + SET_BIT( TIM3->CR1,TIM_CR1_CEN ); + SET_BIT( TIM3->CCER,TIM_CCER_CC2E ); + } + else + { + CLEAR_BIT( TIM3->CCER,TIM_CCER_CC2E ); + CLEAR_BIT( TIM3->CR1, TIM_CR1_CEN ); + } +} +/******************************** ¹¦ÄÜ˵Ã÷ ************************************* +* DIR +*******************************************************************************/ + +//void TIM4_CH1_DIR( _Bool CMD ) +//{ +// if( CMD ) +// { +// GPIO_SetBits( GPIOD, GPIO_ODR_ODR13 ); +// } +// else +// { +// GPIO_ResetBits( GPIOD, GPIO_ODR_ODR13 ); +// } +//} +/******************************** ¹¦ÄÜ˵Ã÷ ************************************* +* +*******************************************************************************/ +void TIM3_IECMD( _Bool CMD ) +{ + if( CMD ) + { + SET_BIT(TIM3->DIER, TIM_DIER_CC2IE); // ʹÄÜÖÐ¶Ï + CLEAR_BIT( TIM3->SR, TIM_SR_UIF | TIM_SR_CC2IF ); // Çå³ýÖжϱê¼Ç + + } + else + { + CLEAR_BIT(TIM3->DIER,TIM_DIER_CC1IE); // ʧÄÜÖÐ¶Ï + CLEAR_BIT( TIM3->SR, TIM_SR_UIF | TIM_SR_CC2IF ); // Çå³ýÖжϱê¼Ç + } +} diff --git a/Core/Src/freertos.c b/Core/Src/freertos.c new file mode 100644 index 0000000..ac67769 --- /dev/null +++ b/Core/Src/freertos.c @@ -0,0 +1,59 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : freertos.c + * Description : Code for freertos applications + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "FreeRTOS.h" +#include "task.h" +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN Variables */ + +/* USER CODE END Variables */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN FunctionPrototypes */ + +/* USER CODE END FunctionPrototypes */ + +/* Private application code --------------------------------------------------*/ +/* USER CODE BEGIN Application */ + +/* USER CODE END Application */ + diff --git a/Core/Src/main.c b/Core/Src/main.c new file mode 100644 index 0000000..c9205f1 --- /dev/null +++ b/Core/Src/main.c @@ -0,0 +1,532 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "cmsis_os.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "APPDEF.H" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc1; +DMA_HandleTypeDef hdma_adc1; + +TIM_HandleTypeDef htim3; +TIM_HandleTypeDef htim4; + +/* Definitions for defaultTask */ +osThreadId_t defaultTaskHandle; +const osThreadAttr_t defaultTask_attributes = { + .name = "defaultTask", + .stack_size = 128 * 4, + .priority = (osPriority_t) osPriorityNormal, +}; +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_DMA_Init(void); +static void MX_ADC1_Init(void); +static void MX_TIM3_Init(void); +static void MX_TIM4_Init(void); +void StartDefaultTask(void *argument); + +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +uint32_t step = 100; +uint32_t ADCDataBuf[10]; +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_DMA_Init(); + MX_ADC1_Init(); + MX_TIM3_Init(); + MX_TIM4_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Init scheduler */ + osKernelInitialize(); + + /* USER CODE BEGIN RTOS_MUTEX */ + /* add mutexes, ... */ + /* USER CODE END RTOS_MUTEX */ + + /* USER CODE BEGIN RTOS_SEMAPHORES */ + /* add semaphores, ... */ + /* USER CODE END RTOS_SEMAPHORES */ + + /* USER CODE BEGIN RTOS_TIMERS */ + /* start timers, add new ones, ... */ + /* USER CODE END RTOS_TIMERS */ + + /* USER CODE BEGIN RTOS_QUEUES */ + /* add queues, ... */ + /* USER CODE END RTOS_QUEUES */ + + /* Create the thread(s) */ + /* creation of defaultTask */ + defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); + + /* USER CODE BEGIN RTOS_THREADS */ + /* add threads, ... */ + /* USER CODE END RTOS_THREADS */ + + /* USER CODE BEGIN RTOS_EVENTS */ + /* add events, ... */ + /* USER CODE END RTOS_EVENTS */ + + /* Start scheduler */ + osKernelStart(); + + /* We should never get here as control is now taken by the scheduler */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; + PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ADC1 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + + /** Common config + */ + hadc1.Instance = ADC1; + hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; + hadc1.Init.ContinuousConvMode = ENABLE; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.NbrOfConversion = 1; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_0; + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + +/** + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) +{ + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + htim3.Init.Prescaler = 72; + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + htim3.Init.Period = 999; + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 499; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + HAL_TIM_MspPostInit(&htim3); + +} + +/** + * @brief TIM4 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM4_Init(void) +{ + + /* USER CODE BEGIN TIM4_Init 0 */ + + /* USER CODE END TIM4_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM4_Init 1 */ + + /* USER CODE END TIM4_Init 1 */ + htim4.Instance = TIM4; + htim4.Init.Prescaler = 72; + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + htim4.Init.Period = 999; + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 499; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM4_Init 2 */ + + /* USER CODE END TIM4_Init 2 */ + HAL_TIM_MspPostInit(&htim4); + +} + +/** + * Enable DMA controller clock + */ +static void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA1_Channel1_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ +float ADCData; +float slope1,slope2; +float SetmL,UseuL; +_Bool CuiQuFlag = false; +_Bool ZhongHeFlag = false; + + + + + +/* USER CODE END 4 */ + +/* USER CODE BEGIN Header_StartDefaultTask */ +/** + * @brief Function implementing the defaultTask thread. + * @param argument: Not used + * @retval None + */ +/* USER CODE END Header_StartDefaultTask */ +void StartDefaultTask(void *argument) +{ + /* USER CODE BEGIN 5 */ + /* Infinite loop */ +// HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_1); +// HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2); + MotorCTRLInitiate(); + HAL_ADCEx_Calibration_Start(&hadc1); + HAL_ADC_Start_DMA( &hadc1,ADCDataBuf,20); + slope1 = 82700; + slope2 = 0.01166; + for(;;) + { + osDelay(500); + if(ZhongHeFlag) + { + CoordinateSet[0] = 6550000; + UseuL = PluseCount[0] * slope2; + } + else + { + CoordinateSet[0] = 0; + } + if(CuiQuFlag) + { + + CoordinateSet[1] = SetmL *slope1; + CuiQuFlag = false; + } + + ADCData = ( + (ADCDataBuf[0] >> 16) + (uint16_t)ADCDataBuf[0] + + (ADCDataBuf[1] >> 16) + (uint16_t)ADCDataBuf[1] + + (ADCDataBuf[2] >> 16) + (uint16_t)ADCDataBuf[2] + + (ADCDataBuf[3] >> 16) + (uint16_t)ADCDataBuf[3] + + (ADCDataBuf[4] >> 16) + (uint16_t)ADCDataBuf[4] + + (ADCDataBuf[5] >> 16) + (uint16_t)ADCDataBuf[5] + + (ADCDataBuf[6] >> 16) + (uint16_t)ADCDataBuf[6] + + (ADCDataBuf[7] >> 16) + (uint16_t)ADCDataBuf[7] + + (ADCDataBuf[8] >> 16) + (uint16_t)ADCDataBuf[8] + + (ADCDataBuf[9] >> 16) + (uint16_t)ADCDataBuf[9] ) / 20; + +// if(CoordinateSet[0] == 0) +// CoordinateSet[0] = step; + } + /* USER CODE END 5 */ +} + +/** + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM1 interrupt took place, inside + * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM1) + { + HAL_IncTick(); + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/Core/Src/stm32f1xx_hal_msp.c b/Core/Src/stm32f1xx_hal_msp.c new file mode 100644 index 0000000..55fc96b --- /dev/null +++ b/Core/Src/stm32f1xx_hal_msp.c @@ -0,0 +1,293 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f1xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ +extern DMA_HandleTypeDef hdma_adc1; + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_AFIO_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); + + /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled + */ + __HAL_AFIO_REMAP_SWJ_NOJTAG(); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** + * @brief ADC MSP Initialization + * This function configures the hardware resources used in this example + * @param hadc: ADC handle pointer + * @retval None + */ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PA0-WKUP ------> ADC1_IN0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* ADC1 DMA Init */ + /* ADC1 Init */ + hdma_adc1.Instance = DMA1_Channel1; + hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; + hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_adc1.Init.Mode = DMA_CIRCULAR; + hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM; + if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + + } + +} + +/** + * @brief ADC MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hadc: ADC handle pointer + * @retval None + */ +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC1_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PA0-WKUP ------> ADC1_IN0 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0); + + /* ADC1 DMA DeInit */ + HAL_DMA_DeInit(hadc->DMA_Handle); + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } + +} + +/** + * @brief TIM_Base MSP Initialization + * This function configures the hardware resources used in this example + * @param htim_base: TIM_Base handle pointer + * @retval None + */ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + /* TIM3 interrupt Init */ + HAL_NVIC_SetPriority(TIM3_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(TIM3_IRQn); + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspInit 0 */ + + /* USER CODE END TIM4_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM4_CLK_ENABLE(); + /* TIM4 interrupt Init */ + HAL_NVIC_SetPriority(TIM4_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(TIM4_IRQn); + /* USER CODE BEGIN TIM4_MspInit 1 */ + + /* USER CODE END TIM4_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspPostInit 0 */ + + /* USER CODE END TIM3_MspPostInit 0 */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**TIM3 GPIO Configuration + PB5 ------> TIM3_CH2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + __HAL_AFIO_REMAP_TIM3_PARTIAL(); + + /* USER CODE BEGIN TIM3_MspPostInit 1 */ + + /* USER CODE END TIM3_MspPostInit 1 */ + } + else if(htim->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspPostInit 0 */ + + /* USER CODE END TIM4_MspPostInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**TIM4 GPIO Configuration + PB6 ------> TIM4_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM4_MspPostInit 1 */ + + /* USER CODE END TIM4_MspPostInit 1 */ + } + +} +/** + * @brief TIM_Base MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param htim_base: TIM_Base handle pointer + * @retval None + */ +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspDeInit 0 */ + + /* USER CODE END TIM3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM3_CLK_DISABLE(); + + /* TIM3 interrupt DeInit */ + HAL_NVIC_DisableIRQ(TIM3_IRQn); + /* USER CODE BEGIN TIM3_MspDeInit 1 */ + + /* USER CODE END TIM3_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspDeInit 0 */ + + /* USER CODE END TIM4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM4_CLK_DISABLE(); + + /* TIM4 interrupt DeInit */ + HAL_NVIC_DisableIRQ(TIM4_IRQn); + /* USER CODE BEGIN TIM4_MspDeInit 1 */ + + /* USER CODE END TIM4_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/stm32f1xx_hal_timebase_tim.c b/Core/Src/stm32f1xx_hal_timebase_tim.c new file mode 100644 index 0000000..b13fcaf --- /dev/null +++ b/Core/Src/stm32f1xx_hal_timebase_tim.c @@ -0,0 +1,129 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f1xx_hal_timebase_tim.c + * @brief HAL time base based on the hardware TIM. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" +#include "stm32f1xx_hal_tim.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_HandleTypeDef htim1; +/* Private function prototypes -----------------------------------------------*/ +void TIM1_IRQHandler(void); +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the TIM1 as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock = 0U; + + uint32_t uwPrescalerValue = 0U; + uint32_t pFLatency; + + HAL_StatusTypeDef status = HAL_OK; + + /* Enable TIM1 clock */ + __HAL_RCC_TIM1_CLK_ENABLE(); + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + + /* Compute TIM1 clock */ + uwTimclock = HAL_RCC_GetPCLK2Freq(); + + /* Compute the prescaler value to have TIM1 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); + + /* Initialize TIM1 */ + htim1.Instance = TIM1; + + /* Initialize TIMx peripheral as follow: + * Period = [(TIM1CLK/1000) - 1]. to have a (1/1000) s time base. + * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + * ClockDivision = 0 + * Counter direction = Up + */ + htim1.Init.Period = (1000000U / 1000U) - 1U; + htim1.Init.Prescaler = uwPrescalerValue; + htim1.Init.ClockDivision = 0; + htim1.Init.CounterMode = TIM_COUNTERMODE_UP; + htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + + status = HAL_TIM_Base_Init(&htim1); + if (status == HAL_OK) + { + /* Start the TIM time Base generation in interrupt mode */ + status = HAL_TIM_Base_Start_IT(&htim1); + if (status == HAL_OK) + { + /* Enable the TIM1 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM1_UP_IRQn); + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Configure the TIM IRQ priority */ + HAL_NVIC_SetPriority(TIM1_UP_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling TIM1 update interrupt. + * @param None + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable TIM1 update Interrupt */ + __HAL_TIM_DISABLE_IT(&htim1, TIM_IT_UPDATE); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by Enabling TIM1 update interrupt. + * @param None + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Enable TIM1 Update interrupt */ + __HAL_TIM_ENABLE_IT(&htim1, TIM_IT_UPDATE); +} + diff --git a/Core/Src/stm32f1xx_it.c b/Core/Src/stm32f1xx_it.c new file mode 100644 index 0000000..7135c88 --- /dev/null +++ b/Core/Src/stm32f1xx_it.c @@ -0,0 +1,245 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f1xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f1xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +extern volatile uint32_t SetPluseCount[7u]; // �������������� +extern volatile uint32_t PluseCount[7u]; // ʵ������������ +extern volatile _Bool CountOver[7u]; // �����������־ +extern void TIM3_CH2_CMD( _Bool CMD ); +extern void TIM4_CH1_CMD( _Bool CMD ); +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern DMA_HandleTypeDef hdma_adc1; +extern TIM_HandleTypeDef htim3; +extern TIM_HandleTypeDef htim4; +extern TIM_HandleTypeDef htim1; + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M3 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F1xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f1xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles DMA1 channel1 global interrupt. + */ +void DMA1_Channel1_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ + + /* USER CODE END DMA1_Channel1_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_adc1); + /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ + + /* USER CODE END DMA1_Channel1_IRQn 1 */ +} + +/** + * @brief This function handles TIM1 update interrupt. + */ +void TIM1_UP_IRQHandler(void) +{ + /* USER CODE BEGIN TIM1_UP_IRQn 0 */ + + /* USER CODE END TIM1_UP_IRQn 0 */ + HAL_TIM_IRQHandler(&htim1); + /* USER CODE BEGIN TIM1_UP_IRQn 1 */ + + /* USER CODE END TIM1_UP_IRQn 1 */ +} + +/** + * @brief This function handles TIM3 global interrupt. + */ +void TIM3_IRQHandler(void) +{ + /* USER CODE BEGIN TIM3_IRQn 0 */ + + /* USER CODE END TIM3_IRQn 0 */ + HAL_TIM_IRQHandler(&htim3); + /* USER CODE BEGIN TIM3_IRQn 1 */ + CLEAR_BIT( TIM3->SR, TIM_SR_UIF | TIM_SR_CC2IF ); // ����жϱ�� + if( PluseCount[1u] < SetPluseCount[1u] ) + PluseCount[1u] ++; + else + { + TIM3_CH2_CMD( 0 ); + CountOver[1u] = 1; + CLEAR_BIT( TIM3->SR, TIM_SR_UIF | TIM_SR_CC2IF ); // ����жϱ�� + } + /* USER CODE END TIM3_IRQn 1 */ +} + +/** + * @brief This function handles TIM4 global interrupt. + */ +void TIM4_IRQHandler(void) +{ + /* USER CODE BEGIN TIM4_IRQn 0 */ + + /* USER CODE END TIM4_IRQn 0 */ + HAL_TIM_IRQHandler(&htim4); + /* USER CODE BEGIN TIM4_IRQn 1 */ + CLEAR_BIT( TIM4->SR, TIM_SR_UIF | TIM_SR_CC1IF ); // ����жϱ�� + if( PluseCount[0u] < SetPluseCount[0u] ) + PluseCount[0u] ++; + else + { + TIM4_CH1_CMD( 0 ); + CountOver[0u] = 1; + CLEAR_BIT( TIM4->SR, TIM_SR_UIF | TIM_SR_CC1IF ); // ����жϱ�� + } + + /* USER CODE END TIM4_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/system_stm32f1xx.c b/Core/Src/system_stm32f1xx.c new file mode 100644 index 0000000..3afa78d --- /dev/null +++ b/Core/Src/system_stm32f1xx.c @@ -0,0 +1,406 @@ +/** + ****************************************************************************** + * @file system_stm32f1xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f1xx_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE". + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f1xx_system + * @{ + */ + +/** @addtogroup STM32F1xx_System_Private_Includes + * @{ + */ + +#include "stm32f1xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Defines + * @{ + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +/*!< Uncomment the following line if you need to use external SRAM */ +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 8000000; +const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; + +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; +#endif /* STM32F105xC */ + +#if defined(STM32F100xB) || defined(STM32F100xE) + uint32_t prediv1factor = 0U; +#endif /* STM32F100xB or STM32F100xE */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00U: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04U: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08U: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#if !defined(STM32F105xC) && !defined(STM32F107xC) + pllmull = ( pllmull >> 18U) + 2U; + + if (pllsource == 0x00U) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; + } + else + { + #if defined(STM32F100xB) || defined(STM32F100xE) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18U; + + if (pllmull != 0x0DU) + { + pllmull += 2U; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13U / 2U; + } + + if (pllsource == 0x00U) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; + + if (prediv1source == 0U) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F105xC */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +/** + * @brief Setup the external memory controller. Called in startup_stm32f1xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f1xx_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmpreg; + /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114U; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0U; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); + + (void)(tmpreg); + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BBU; + GPIOD->CRH = 0xBBBBBBBBU; + + GPIOE->CRL = 0xB44444BBU; + GPIOE->CRH = 0xBBBBBBBBU; + + GPIOF->CRL = 0x44BBBBBBU; + GPIOF->CRH = 0xBBBB4444U; + + GPIOG->CRL = 0x44BBBBBBU; + GPIOG->CRH = 0x444B4B44U; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4U] = 0x00001091U; + FSMC_Bank1->BTCR[5U] = 0x00110212U; +} +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/MDK-ARM/YouSuan.uvoptx b/MDK-ARM/YouSuan.uvoptx new file mode 100644 index 0000000..44098a5 --- /dev/null +++ b/MDK-ARM/YouSuan.uvoptx @@ -0,0 +1,765 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + YouSuan + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\OutPut\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + DLGDARM + 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