552 lines
118 KiB
Plaintext
552 lines
118 KiB
Plaintext
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Protel Design System Design Rule Check
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PCB File : C:\Users\g\Desktop\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\6.Ӳ<><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\1.<2E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\MAIN-BOARD.PcbDoc
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Date : 2025/10/14
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Time : 15:03:45
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ERROR : More than 500 violations detected, DRC was stopped
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Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
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Rule Violations :0
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Processing Rule : Un-Routed Net Constraint ( (All) )
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=7mil) (All),(All)
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Rule Violations :0
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Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
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Rule Violations :0
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Processing Rule : Width Constraint (Min=10mil) (Max=236.22mil) (Preferred=10mil) (All)
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Rule Violations :0
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Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
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Rule Violations :0
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Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
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Rule Violations :0
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Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
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Rule Violations :0
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Processing Rule : Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
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Violation between Minimum Solder Mask Sliver Constraint: (6mil < 10mil) Between Pad R3-1(2794mil,2895mil) on Top Layer And Pad R1-1(2740mil,2895mil) on Top Layer [Top Solder] Mask Sliver [6mil]
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Violation between Minimum Solder Mask Sliver Constraint: (6mil < 10mil) Between Pad R3-2(2794mil,2829mil) on Top Layer And Pad R1-2(2740mil,2829mil) on Top Layer [Top Solder] Mask Sliver [6mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.107mil < 10mil) Between Via (3472mil,719mil) from Top Layer to Bottom Layer And Pad U11-1(3472mil,663mil) on Top Layer [Top Solder] Mask Sliver [3.107mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.787mil < 10mil) Between Via (3900mil,480mil) from Top Layer to Bottom Layer And Pad U11-4(3838mil,463mil) on Top Layer [Top Solder] Mask Sliver [4.787mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.793mil < 10mil) Between Via (716mil,3129mil) from Top Layer to Bottom Layer And Pad D6-2(751mil,3189.94mil) on Top Layer [Top Solder] Mask Sliver [4.793mil]
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Violation between Minimum Solder Mask Sliver Constraint: (7.793mil < 10mil) Between Via (789mil,3126mil) from Top Layer to Bottom Layer And Pad D6-2(751mil,3189.94mil) on Top Layer [Top Solder] Mask Sliver [7.793mil]
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Violation between Minimum Solder Mask Sliver Constraint: (1.913mil < 10mil) Between Via (727mil,3248mil) from Top Layer to Bottom Layer And Pad D6-2(751mil,3189.94mil) on Top Layer [Top Solder] Mask Sliver [1.913mil]
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Violation between Minimum Solder Mask Sliver Constraint: (9.793mil < 10mil) Between Via (751mil,3124mil) from Top Layer to Bottom Layer And Pad D6-2(751mil,3189.94mil) on Top Layer [Top Solder] Mask Sliver [9.793mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.913mil < 10mil) Between Via (784mil,3250mil) from Top Layer to Bottom Layer And Pad D6-2(751mil,3189.94mil) on Top Layer [Top Solder] Mask Sliver [3.913mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4mil < 10mil) Between Pad R72-1(1421mil,3096.001mil) on Top Layer And Pad R56-1(1369mil,3096.001mil) on Top Layer [Top Solder] Mask Sliver [4mil]
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Violation between Minimum Solder Mask Sliver Constraint: (2.188mil < 10mil) Between Via (1344mil,3138mil) from Top Layer to Bottom Layer And Pad R56-1(1369mil,3096.001mil) on Top Layer [Top Solder] Mask Sliver [2.188mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4mil < 10mil) Between Pad R72-2(1421mil,3030.001mil) on Top Layer And Pad R56-2(1369mil,3030.001mil) on Top Layer [Top Solder] Mask Sliver [4mil]
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Violation between Minimum Solder Mask Sliver Constraint: (5.132mil < 10mil) Between Via (1327mil,2998mil) from Top Layer to Bottom Layer And Pad R56-2(1369mil,3030.001mil) on Top Layer [Top Solder] Mask Sliver [5.132mil]
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Violation between Minimum Solder Mask Sliver Constraint: (5.855mil < 10mil) Between Via (126mil,1159mil) from Top Layer to Bottom Layer And Pad C40-2(160.001mil,1201mil) on Top Layer [Top Solder] Mask Sliver [5.855mil]
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Violation between Minimum Solder Mask Sliver Constraint: (7.853mil < 10mil) Between Via (264mil,3332mil) from Top Layer to Bottom Layer And Pad D5-1(316.98mil,3400mil) on Top Layer [Top Solder] Mask Sliver [7.853mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U13-2(1276.78mil,1055mil) on Top Layer And Pad U13-1(1302.37mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U13-3(1251.19mil,1055mil) on Top Layer And Pad U13-2(1276.78mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.096mil < 10mil) Between Pad U13-4(1225.59mil,1055mil) on Top Layer And Pad U13-3(1251.19mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.096mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U13-5(1200mil,1055mil) on Top Layer And Pad U13-4(1225.59mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U13-6(1174.41mil,1055mil) on Top Layer And Pad U13-5(1200mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U13-7(1148.82mil,1055mil) on Top Layer And Pad U13-6(1174.41mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U13-8(1123.23mil,1055mil) on Top Layer And Pad U13-7(1148.82mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U13-15(1276.78mil,829.35mil) on Top Layer And Pad U13-16(1302.37mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U13-14(1251.19mil,829.35mil) on Top Layer And Pad U13-15(1276.78mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.096mil < 10mil) Between Pad U13-13(1225.59mil,829.35mil) on Top Layer And Pad U13-14(1251.19mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.096mil]
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Violation between Minimum Solder Mask Sliver Constraint: (9.916mil < 10mil) Between Via (1257mil,768mil) from Top Layer to Bottom Layer And Pad U13-14(1251.19mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [9.916mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U13-12(1200mil,829.35mil) on Top Layer And Pad U13-13(1225.59mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U13-11(1174.41mil,829.35mil) on Top Layer And Pad U13-12(1200mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U13-10(1148.82mil,829.35mil) on Top Layer And Pad U13-11(1174.41mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U13-9(1123.23mil,829.35mil) on Top Layer And Pad U13-10(1148.82mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U9-2(621.78mil,1055mil) on Top Layer And Pad U9-1(647.37mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U9-3(596.19mil,1055mil) on Top Layer And Pad U9-2(621.78mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.096mil < 10mil) Between Pad U9-4(570.59mil,1055mil) on Top Layer And Pad U9-3(596.19mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.096mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U9-5(545mil,1055mil) on Top Layer And Pad U9-4(570.59mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U9-6(519.41mil,1055mil) on Top Layer And Pad U9-5(545mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U9-7(493.82mil,1055mil) on Top Layer And Pad U9-6(519.41mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U9-8(468.23mil,1055mil) on Top Layer And Pad U9-7(493.82mil,1055mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U9-15(621.78mil,829.35mil) on Top Layer And Pad U9-16(647.37mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U9-14(596.19mil,829.35mil) on Top Layer And Pad U9-15(621.78mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.096mil < 10mil) Between Pad U9-13(570.59mil,829.35mil) on Top Layer And Pad U9-14(596.19mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.096mil]
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Violation between Minimum Solder Mask Sliver Constraint: (7.649mil < 10mil) Between Via (600mil,770mil) from Top Layer to Bottom Layer And Pad U9-14(596.19mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [7.649mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U9-12(545mil,829.35mil) on Top Layer And Pad U9-13(570.59mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U9-11(519.41mil,829.35mil) on Top Layer And Pad U9-12(545mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U9-10(493.82mil,829.35mil) on Top Layer And Pad U9-11(519.41mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (4.086mil < 10mil) Between Pad U9-9(468.23mil,829.35mil) on Top Layer And Pad U9-10(493.82mil,829.35mil) on Top Layer [Top Solder] Mask Sliver [4.086mil]
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Violation between Minimum Solder Mask Sliver Constraint: (9.83mil < 10mil) Between Pad U8-2(188.005mil,1414.307mil) on Top Layer And Pad U8-1(225.395mil,1414.307mil) on Top Layer [Top Solder] Mask Sliver [9.83mil]
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Violation between Minimum Solder Mask Sliver Constraint: (9.84mil < 10mil) Between Pad U8-2(188.005mil,1414.307mil) on Top Layer And Pad U8-3(150.605mil,1414.307mil) on Top Layer [Top Solder] Mask Sliver [9.84mil]
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Violation between Minimum Solder Mask Sliver Constraint: (9.691mil < 10mil) Between Via (825mil,1959mil) from Top Layer to Bottom Layer And Pad U7-1(900mil,1993.55mil) on Top Layer [Top Solder] Mask Sliver [9.691mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.81mil < 10mil) Between Pad U4-27(1377.574mil,3387mil) on Top Layer And Pad U4-28(1357.89mil,3387mil) on Top Layer [Top Solder] Mask Sliver [3.81mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.812mil < 10mil) Between Pad U4-26(1397.26mil,3387mil) on Top Layer And Pad U4-27(1377.574mil,3387mil) on Top Layer [Top Solder] Mask Sliver [3.812mil]
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Violation between Minimum Solder Mask Sliver Constraint: (6.973mil < 10mil) Between Via (1349mil,3416mil) from Top Layer to Bottom Layer And Pad U4-27(1377.574mil,3387mil) on Top Layer [Top Solder] Mask Sliver [6.973mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.81mil < 10mil) Between Pad U4-25(1416.944mil,3387mil) on Top Layer And Pad U4-26(1397.26mil,3387mil) on Top Layer [Top Solder] Mask Sliver [3.81mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.812mil < 10mil) Between Pad U4-24(1436.63mil,3387mil) on Top Layer And Pad U4-25(1416.944mil,3387mil) on Top Layer [Top Solder] Mask Sliver [3.812mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.81mil < 10mil) Between Pad U4-23(1456.314mil,3387mil) on Top Layer And Pad U4-24(1436.63mil,3387mil) on Top Layer [Top Solder] Mask Sliver [3.81mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.812mil < 10mil) Between Pad U4-22(1476mil,3387mil) on Top Layer And Pad U4-23(1456.314mil,3387mil) on Top Layer [Top Solder] Mask Sliver [3.812mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.812mil < 10mil) Between Pad U4-20(1515mil,3328.424mil) on Top Layer And Pad U4-21(1515mil,3348.11mil) on Top Layer [Top Solder] Mask Sliver [3.812mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.81mil < 10mil) Between Pad U4-19(1515mil,3308.74mil) on Top Layer And Pad U4-20(1515mil,3328.424mil) on Top Layer [Top Solder] Mask Sliver [3.81mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.812mil < 10mil) Between Pad U4-18(1515mil,3289.054mil) on Top Layer And Pad U4-19(1515mil,3308.74mil) on Top Layer [Top Solder] Mask Sliver [3.812mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.81mil < 10mil) Between Pad U4-17(1515mil,3269.37mil) on Top Layer And Pad U4-18(1515mil,3289.054mil) on Top Layer [Top Solder] Mask Sliver [3.81mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.812mil < 10mil) Between Pad U4-16(1515mil,3249.684mil) on Top Layer And Pad U4-17(1515mil,3269.37mil) on Top Layer [Top Solder] Mask Sliver [3.812mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.81mil < 10mil) Between Pad U4-15(1515mil,3230mil) on Top Layer And Pad U4-16(1515mil,3249.684mil) on Top Layer [Top Solder] Mask Sliver [3.81mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.812mil < 10mil) Between Pad U4-13(1455.424mil,3191mil) on Top Layer And Pad U4-14(1475.11mil,3191mil) on Top Layer [Top Solder] Mask Sliver [3.812mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.81mil < 10mil) Between Pad U4-12(1435.74mil,3191mil) on Top Layer And Pad U4-13(1455.424mil,3191mil) on Top Layer [Top Solder] Mask Sliver [3.81mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.812mil < 10mil) Between Pad U4-11(1416.054mil,3191mil) on Top Layer And Pad U4-12(1435.74mil,3191mil) on Top Layer [Top Solder] Mask Sliver [3.812mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.81mil < 10mil) Between Pad U4-10(1396.37mil,3191mil) on Top Layer And Pad U4-11(1416.054mil,3191mil) on Top Layer [Top Solder] Mask Sliver [3.81mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.812mil < 10mil) Between Pad U4-9(1376.684mil,3191mil) on Top Layer And Pad U4-10(1396.37mil,3191mil) on Top Layer [Top Solder] Mask Sliver [3.812mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.81mil < 10mil) Between Pad U4-8(1357mil,3191mil) on Top Layer And Pad U4-9(1376.684mil,3191mil) on Top Layer [Top Solder] Mask Sliver [3.81mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.81mil < 10mil) Between Pad U4-6(1318mil,3249.574mil) on Top Layer And Pad U4-7(1318mil,3229.89mil) on Top Layer [Top Solder] Mask Sliver [3.81mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.812mil < 10mil) Between Pad U4-5(1318mil,3269.26mil) on Top Layer And Pad U4-6(1318mil,3249.574mil) on Top Layer [Top Solder] Mask Sliver [3.812mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.81mil < 10mil) Between Pad U4-4(1318mil,3288.944mil) on Top Layer And Pad U4-5(1318mil,3269.26mil) on Top Layer [Top Solder] Mask Sliver [3.81mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.812mil < 10mil) Between Pad U4-3(1318mil,3308.63mil) on Top Layer And Pad U4-4(1318mil,3288.944mil) on Top Layer [Top Solder] Mask Sliver [3.812mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.81mil < 10mil) Between Pad U4-2(1318mil,3328.314mil) on Top Layer And Pad U4-3(1318mil,3308.63mil) on Top Layer [Top Solder] Mask Sliver [3.81mil]
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Violation between Minimum Solder Mask Sliver Constraint: (8.976mil < 10mil) Between Via (1270mil,3314mil) from Top Layer to Bottom Layer And Pad U4-3(1318mil,3308.63mil) on Top Layer [Top Solder] Mask Sliver [8.976mil]
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Violation between Minimum Solder Mask Sliver Constraint: (3.812mil < 10mil) Between Pad U4-1(1318mil,3348mil) on Top Layer And Pad U4-2(1318mil,3328.314mil) on Top Layer [Top Solder] Mask Sliver [3.812mil]
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Violation between Minimum Solder Mask Sliver Constraint: (6.36mil < 10mil) Between Via (1982mil,1703mil) from Top Layer to Bottom Layer And Pad U3-32(2043.63mil,1692.36mil) on Top Layer [Top Solder] Mask Sliver [6.36mil]
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Violation between Minimum Solder Mask Sliver Constraint: (5.836mil < 10mil) Between Via (1982mil,1703mil) from Top Layer to Bottom Layer And Pad U3-31(2043.63mil,1712.05mil) on Top Layer [Top Solder] Mask Sliver [5.836mil]
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Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R61-1(1130mil,1368.001mil) on Top Layer And Pad R66-1(1185mil,1368.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
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Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R63-1(1240mil,1368.001mil) on Top Layer And Pad R66-1(1185mil,1368.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
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Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R61-2(1130mil,1302.001mil) on Top Layer And Pad R66-2(1185mil,1302.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
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Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R63-2(1240mil,1302.001mil) on Top Layer And Pad R66-2(1185mil,1302.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
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Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R62-1(1295mil,1368.001mil) on Top Layer And Pad R63-1(1240mil,1368.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R62-2(1295mil,1302.001mil) on Top Layer And Pad R63-2(1240mil,1302.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R59-1(1075mil,1368.001mil) on Top Layer And Pad R61-1(1130mil,1368.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R59-2(1075mil,1302.001mil) on Top Layer And Pad R61-2(1130mil,1302.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R58-1(1193.39mil,635.826mil) on Top Layer And Pad R60-1(1138.39mil,635.826mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7.001mil < 10mil) Between Pad C57-2(1083.39mil,635.824mil) on Top Layer And Pad R60-1(1138.39mil,635.826mil) on Top Layer [Top Solder] Mask Sliver [7.001mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R58-2(1193.39mil,569.826mil) on Top Layer And Pad R60-2(1138.39mil,569.826mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7.001mil < 10mil) Between Pad C57-1(1083.39mil,569.824mil) on Top Layer And Pad R60-2(1138.39mil,569.826mil) on Top Layer [Top Solder] Mask Sliver [7.001mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad C55-1(1248.39mil,635.826mil) on Top Layer And Pad R58-1(1193.39mil,635.826mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad C55-2(1248.39mil,569.826mil) on Top Layer And Pad R58-2(1193.39mil,569.826mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (5.115mil < 10mil) Between Via (877mil,1023mil) from Top Layer to Bottom Layer And Pad R52-1(908.39mil,980.824mil) on Top Layer [Top Solder] Mask Sliver [5.115mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (9mil < 10mil) Between Pad R55-1(3293mil,854mil) on Top Layer And Pad R57-1(3236mil,855mil) on Top Layer [Top Solder] Mask Sliver [9mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (9mil < 10mil) Between Pad R55-2(3293mil,788mil) on Top Layer And Pad R57-2(3236mil,789mil) on Top Layer [Top Solder] Mask Sliver [9mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (9.178mil < 10mil) Between Via (877mil,1023mil) from Top Layer to Bottom Layer And Pad R48-1(840mil,978.001mil) on Top Layer [Top Solder] Mask Sliver [9.178mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R38-1(475mil,1368.001mil) on Top Layer And Pad R41-1(530mil,1368.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R40-1(585mil,1368.001mil) on Top Layer And Pad R41-1(530mil,1368.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R38-2(475mil,1302.001mil) on Top Layer And Pad R41-2(530mil,1302.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R40-2(585mil,1302.001mil) on Top Layer And Pad R41-2(530mil,1302.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R39-1(640mil,1368.001mil) on Top Layer And Pad R40-1(585mil,1368.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R39-2(640mil,1302.001mil) on Top Layer And Pad R40-2(585mil,1302.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R36-1(420mil,1368.001mil) on Top Layer And Pad R38-1(475mil,1368.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R36-2(420mil,1302.001mil) on Top Layer And Pad R38-2(475mil,1302.001mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7.001mil < 10mil) Between Pad C48-2(428.39mil,635.824mil) on Top Layer And Pad R37-1(483.39mil,635.826mil) on Top Layer [Top Solder] Mask Sliver [7.001mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R35-1(538.39mil,635.826mil) on Top Layer And Pad R37-1(483.39mil,635.826mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7.001mil < 10mil) Between Pad C48-1(428.39mil,569.824mil) on Top Layer And Pad R37-2(483.39mil,569.826mil) on Top Layer [Top Solder] Mask Sliver [7.001mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad R35-2(538.39mil,569.826mil) on Top Layer And Pad R37-2(483.39mil,569.826mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad C46-1(593.39mil,635.826mil) on Top Layer And Pad R35-1(538.39mil,635.826mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad C46-2(593.39mil,569.826mil) on Top Layer And Pad R35-2(538.39mil,569.826mil) on Top Layer [Top Solder] Mask Sliver [7mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (4.999mil < 10mil) Between Pad C38-2(154.001mil,1546mil) on Top Layer And Pad R29-1(154.999mil,1493mil) on Top Layer [Top Solder] Mask Sliver [4.999mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (4.999mil < 10mil) Between Pad C38-1(220.001mil,1546mil) on Top Layer And Pad R29-2(220.999mil,1493mil) on Top Layer [Top Solder] Mask Sliver [4.999mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (2mil < 10mil) Between Pad C31-1(438.956mil,2447.001mil) on Top Layer And Pad R27-1(438.956mil,2397.001mil) on Top Layer [Top Solder] Mask Sliver [2mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (2mil < 10mil) Between Pad C31-2(372.956mil,2447.001mil) on Top Layer And Pad R27-2(372.956mil,2397.001mil) on Top Layer [Top Solder] Mask Sliver [2mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7.158mil < 10mil) Between Via (369mil,2352mil) from Top Layer to Bottom Layer And Pad R27-2(372.956mil,2397.001mil) on Top Layer [Top Solder] Mask Sliver [7.158mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (2.001mil < 10mil) Between Pad C31-2(372.956mil,2447.001mil) on Top Layer And Pad R26-1(372.954mil,2497.001mil) on Top Layer [Top Solder] Mask Sliver [2.001mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (2.001mil < 10mil) Between Pad C31-1(438.956mil,2447.001mil) on Top Layer And Pad R26-2(438.954mil,2497.001mil) on Top Layer [Top Solder] Mask Sliver [2.001mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7.999mil < 10mil) Between Pad R15-2(1644mil,3196.001mil) on Top Layer And Pad R17-1(1700mil,3196.999mil) on Top Layer [Top Solder] Mask Sliver [7.999mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (7.999mil < 10mil) Between Pad R15-1(1644mil,3262.001mil) on Top Layer And Pad R17-2(1700mil,3262.999mil) on Top Layer [Top Solder] Mask Sliver [7.999mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (3.158mil < 10mil) Between Via (1642mil,3153mil) from Top Layer to Bottom Layer And Pad R15-2(1644mil,3196.001mil) on Top Layer [Top Solder] Mask Sliver [3.158mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (2mil < 10mil) Between Pad C22-1(1221mil,3279mil) on Top Layer And Pad R13-1(1221mil,3329mil) on Top Layer [Top Solder] Mask Sliver [2mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (9.158mil < 10mil) Between Via (1270mil,3314mil) from Top Layer to Bottom Layer And Pad R13-1(1221mil,3329mil) on Top Layer [Top Solder] Mask Sliver [9.158mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (2mil < 10mil) Between Pad C22-2(1155mil,3279mil) on Top Layer And Pad R13-2(1155mil,3329mil) on Top Layer [Top Solder] Mask Sliver [2mil]
|
|||
|
|
Violation between Minimum Solder Mask Sliver Constraint: (3mil < 10mil) Between Pad C9-1(1822.999mil,1731mil) on Top Layer And Pad R9-1(1821.999mil,1782mil) on Top Layer [Top Solder] Mask Sliver [3mil]
|
|||
|
|
Rule Violations :122
|
|||
|
|
|
|||
|
|
Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.934mil < 10mil) Between Arc (1326.93mil,1055mil) on Top Overlay And Pad U13-1(1302.37mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.934mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.934mil < 10mil) Between Arc (671.93mil,1055mil) on Top Overlay And Pad U9-1(647.37mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.934mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (4.322mil < 10mil) Between Arc (225.804mil,1450.13mil) on Top Overlay And Pad U8-1(225.395mil,1414.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [4.322mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.662mil < 10mil) Between Arc (488.699mil,2732.345mil) on Top Overlay And Pad U5-1(488.699mil,2702.955mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.662mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6.18mil < 10mil) Between Arc (2441.653mil,2062.047mil) on Top Overlay And Pad U3-1(2417.64mil,2066.37mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.18mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.898mil < 10mil) Between Arc (3994.11mil,3329.022mil) on Top Overlay And Pad U2-1(3965mil,3329.022mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.898mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6.62mil < 10mil) Between Arc (5372.75mil,3386.216mil) on Top Overlay And Pad RLY1-1(5307mil,3387mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [6.62mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.031mil < 10mil) Between Arc (1116mil,3486mil) on Top Overlay And Pad R13-2(1155mil,3329mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.031mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.031mil < 10mil) Between Arc (1116mil,3486mil) on Top Overlay And Pad R13-2(1155mil,3329mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.031mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6.003mil < 10mil) Between Arc (4773.2mil,2866.11mil) on Top Overlay And Pad D8-1(4773.2mil,2829mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.003mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (7.392mil < 10mil) Between Arc (172mil,3555mil) on Top Overlay And Pad 8V-1(172mil,3555mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.392mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (7.097mil < 10mil) Between Arc (165.124mil,1858.948mil) on Top Overlay And Pad U6-1(212.845mil,1795.185mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.097mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (7.392mil < 10mil) Between Arc (2155mil,3126mil) on Top Overlay And Pad V5V-1(2155mil,3126mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.392mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (7.392mil < 10mil) Between Arc (3193mil,2070mil) on Top Overlay And Pad 3V3-1(3193mil,2070mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.392mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (7.392mil < 10mil) Between Arc (1762mil,1079mil) on Top Overlay And Pad GND1-1(1762mil,1079mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.392mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (7.392mil < 10mil) Between Arc (119mil,660mil) on Top Overlay And Pad A3V3-1(119mil,660mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.392mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Region (0 hole(s)) Top Overlay And Pad D7-1(5162mil,3614.68mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Region (0 hole(s)) Top Overlay And Pad D7-1(5162mil,3614.68mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.413mil < 10mil) Between Track (5106.834mil,3566.897mil)(5217.166mil,3566.897mil) on Top Overlay And Pad D7-1(5162mil,3614.68mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.413mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5mil < 10mil) Between Track (5106.834mil,3424.668mil)(5122.642mil,3424.668mil) on Top Overlay And Pad D7-2(5162mil,3449.32mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5mil < 10mil) Between Track (5201.358mil,3424.668mil)(5217.166mil,3424.668mil) on Top Overlay And Pad D7-2(5162mil,3449.32mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Track (5111.969mil,837.192mil)(5111.969mil,893.686mil) on Top Overlay And Pad R54-2(5189mil,859.44mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Track (5266.031mil,837.192mil)(5266.031mil,893.686mil) on Top Overlay And Pad R54-2(5189mil,859.44mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Track (5111.969mil,893.686mil)(5266.031mil,893.686mil) on Top Overlay And Pad R54-2(5189mil,859.44mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Track (5111.969mil,583.754mil)(5111.969mil,640.248mil) on Top Overlay And Pad R54-1(5189mil,618mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Track (5266.031mil,583.754mil)(5266.031mil,640.248mil) on Top Overlay And Pad R54-1(5189mil,618mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Track (5111.969mil,583.754mil)(5266.031mil,583.754mil) on Top Overlay And Pad R54-1(5189mil,618mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2726mil,2855mil)(2726mil,2869mil) on Top Overlay And Pad R1-1(2740mil,2895mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2754mil,2855mil)(2754mil,2869mil) on Top Overlay And Pad R1-1(2740mil,2895mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2726mil,2855mil)(2726mil,2869mil) on Top Overlay And Pad R1-2(2740mil,2829mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2754mil,2855mil)(2754mil,2869mil) on Top Overlay And Pad R1-2(2740mil,2829mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (8.735mil < 10mil) Between Text "R1" (2652mil,2838mil) on Top Overlay And Pad R1-2(2740mil,2829mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.735mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3364mil,1490.999mil)(3364mil,1504.999mil) on Top Overlay And Pad R70-1(3350mil,1464.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3336mil,1490.999mil)(3336mil,1504.999mil) on Top Overlay And Pad R70-1(3350mil,1464.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3364mil,1490.999mil)(3364mil,1504.999mil) on Top Overlay And Pad R70-2(3350mil,1530.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3336mil,1490.999mil)(3336mil,1504.999mil) on Top Overlay And Pad R70-2(3350mil,1530.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2.692mil < 10mil) Between Track (3257.913mil,1669.591mil)(3298.528mil,1669.591mil) on Top Overlay And Pad Q6-3(3318mil,1680.37mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2.692mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2.692mil < 10mil) Between Track (3337.472mil,1669.591mil)(3378.087mil,1669.591mil) on Top Overlay And Pad Q6-3(3318mil,1680.37mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2.692mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.907mil < 10mil) Between Track (3378.087mil,1612.409mil)(3378.087mil,1669.591mil) on Top Overlay And Pad Q6-2(3355.4mil,1601.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.907mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2.692mil < 10mil) Between Track (3300.071mil,1612.409mil)(3335.929mil,1612.409mil) on Top Overlay And Pad Q6-2(3355.4mil,1601.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2.692mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.907mil < 10mil) Between Track (3257.913mil,1612.409mil)(3257.913mil,1669.591mil) on Top Overlay And Pad Q6-1(3280.6mil,1601.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.907mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2.692mil < 10mil) Between Track (3300.071mil,1612.409mil)(3335.929mil,1612.409mil) on Top Overlay And Pad Q6-1(3280.6mil,1601.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2.692mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3292mil,1491.999mil)(3292mil,1505.999mil) on Top Overlay And Pad R69-1(3278mil,1465.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3264mil,1491.999mil)(3264mil,1505.999mil) on Top Overlay And Pad R69-1(3278mil,1465.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3292mil,1491.999mil)(3292mil,1505.999mil) on Top Overlay And Pad R69-2(3278mil,1531.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3264mil,1491.999mil)(3264mil,1505.999mil) on Top Overlay And Pad R69-2(3278mil,1531.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5mil < 10mil) Between Track (802.157mil,3205.02mil)(825.26mil,3205.02mil) on Top Overlay And Pad D6-2(751mil,3189.94mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5mil < 10mil) Between Track (676.74mil,3205.02mil)(699.843mil,3205.02mil) on Top Overlay And Pad D6-2(751mil,3189.94mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Region (0 hole(s)) Top Overlay And Pad D6-1(751mil,3004.06mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Region (0 hole(s)) Top Overlay And Pad D6-1(751mil,3004.06mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.643mil < 10mil) Between Track (676.74mil,3057mil)(825.26mil,3057mil) on Top Overlay And Pad D6-1(751mil,3004.06mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.643mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1355mil,3056.001mil)(1355mil,3070.001mil) on Top Overlay And Pad R56-1(1369mil,3096.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1383mil,3056.001mil)(1383mil,3070.001mil) on Top Overlay And Pad R56-1(1369mil,3096.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1355mil,3056.001mil)(1355mil,3070.001mil) on Top Overlay And Pad R56-2(1369mil,3030.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1383mil,3056.001mil)(1383mil,3070.001mil) on Top Overlay And Pad R56-2(1369mil,3030.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1407mil,3056.001mil)(1407mil,3070.001mil) on Top Overlay And Pad R72-1(1421mil,3096.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1435mil,3056.001mil)(1435mil,3070.001mil) on Top Overlay And Pad R72-1(1421mil,3096.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1407mil,3056.001mil)(1407mil,3070.001mil) on Top Overlay And Pad R72-2(1421mil,3030.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1435mil,3056.001mil)(1435mil,3070.001mil) on Top Overlay And Pad R72-2(1421mil,3030.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (186.001mil,1215mil)(200.001mil,1215mil) on Top Overlay And Pad C40-1(226.001mil,1201mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (186.001mil,1187mil)(200.001mil,1187mil) on Top Overlay And Pad C40-1(226.001mil,1201mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (186.001mil,1215mil)(200.001mil,1215mil) on Top Overlay And Pad C40-2(160.001mil,1201mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (186.001mil,1187mil)(200.001mil,1187mil) on Top Overlay And Pad C40-2(160.001mil,1201mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (8.363mil < 10mil) Between Text "C40" (30mil,1181mil) on Top Overlay And Pad C40-2(160.001mil,1201mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.363mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.74mil < 10mil) Between Region (0 hole(s)) Top Overlay And Pad D5-1(316.98mil,3400mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.74mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.74mil < 10mil) Between Region (0 hole(s)) Top Overlay And Pad D5-1(316.98mil,3400mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.74mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6.294mil < 10mil) Between Track (366.579mil,3325.74mil)(366.579mil,3474.26mil) on Top Overlay And Pad D5-1(316.98mil,3400mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.294mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (4.315mil < 10mil) Between Track (366.6mil,3399.7mil)(472.7mil,3399.7mil) on Top Overlay And Pad D5-1(316.98mil,3400mil) on Top Layer [Top Overlay] to [Top Solder] clearance [4.315mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.002mil < 10mil) Between Track (472.713mil,3325.74mil)(472.713mil,3474.26mil) on Top Overlay And Pad D5-2(521.02mil,3400mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.002mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.74mil < 10mil) Between Region (0 hole(s)) Top Overlay And Pad D5-2(521.02mil,3400mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.74mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.74mil < 10mil) Between Region (0 hole(s)) Top Overlay And Pad D5-2(521.02mil,3400mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.74mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.015mil < 10mil) Between Track (366.6mil,3399.7mil)(472.7mil,3399.7mil) on Top Overlay And Pad D5-2(521.02mil,3400mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.015mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2.437mil < 10mil) Between Track (2494.13mil,491.671mil)(2505.94mil,491.671mil) on Top Overlay And Pad V1-K(2463.618mil,491.671mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2.437mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2.437mil < 10mil) Between Track (2518.862mil,491.671mil)(2527.594mil,491.671mil) on Top Overlay And Pad V1-A(2558.106mil,491.671mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2.437mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2594.862mil,719.67mil)(2594.862mil,733.67mil) on Top Overlay And Pad R22-1(2580.862mil,693.67mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2566.862mil,719.67mil)(2566.862mil,733.67mil) on Top Overlay And Pad R22-1(2580.862mil,693.67mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2594.862mil,719.67mil)(2594.862mil,733.67mil) on Top Overlay And Pad R22-2(2580.862mil,759.67mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2566.862mil,719.67mil)(2566.862mil,733.67mil) on Top Overlay And Pad R22-2(2580.862mil,759.67mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2446.862mil,719.672mil)(2446.862mil,733.672mil) on Top Overlay And Pad R19-1(2460.862mil,759.672mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2474.862mil,719.672mil)(2474.862mil,733.672mil) on Top Overlay And Pad R19-1(2460.862mil,759.672mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2446.862mil,719.672mil)(2446.862mil,733.672mil) on Top Overlay And Pad R19-2(2460.862mil,693.672mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2474.862mil,719.672mil)(2474.862mil,733.672mil) on Top Overlay And Pad R19-2(2460.862mil,693.672mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2506.862mil,719.67mil)(2506.862mil,733.67mil) on Top Overlay And Pad R18-1(2520.862mil,693.67mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2534.862mil,719.67mil)(2534.862mil,733.67mil) on Top Overlay And Pad R18-1(2520.862mil,693.67mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2506.862mil,719.67mil)(2506.862mil,733.67mil) on Top Overlay And Pad R18-2(2520.862mil,759.67mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2534.862mil,719.67mil)(2534.862mil,733.67mil) on Top Overlay And Pad R18-2(2520.862mil,759.67mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2073.756mil,722.999mil)(2073.756mil,736.999mil) on Top Overlay And Pad R20-1(2059.756mil,696.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2045.756mil,722.999mil)(2045.756mil,736.999mil) on Top Overlay And Pad R20-1(2059.756mil,696.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2073.756mil,722.999mil)(2073.756mil,736.999mil) on Top Overlay And Pad R20-2(2059.756mil,762.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2045.756mil,722.999mil)(2045.756mil,736.999mil) on Top Overlay And Pad R20-2(2059.756mil,762.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9mil < 10mil) Between Track (2575.862mil,551.671mil)(2581.862mil,557.671mil) on Top Overlay And Pad D1-2(2560.862mil,596.671mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Track (2581.862mil,557.671mil)(2581.862mil,560.671mil) on Top Overlay And Pad D1-2(2560.862mil,596.671mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (2581.862mil,560.671mil)(2588.862mil,567.671mil) on Top Overlay And Pad D1-2(2560.862mil,596.671mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (2588.862mil,567.671mil)(2591.862mil,567.671mil) on Top Overlay And Pad D1-2(2560.862mil,596.671mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (2579.862mil,637.671mil)(2591.862mil,625.671mil) on Top Overlay And Pad D1-2(2560.862mil,596.671mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (2591.862mil,552.671mil)(2591.862mil,641.671mil) on Top Overlay And Pad D1-2(2560.862mil,596.671mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (4mil < 10mil) Between Track (2599.862mil,553.671mil)(2599.862mil,641.671mil) on Top Overlay And Pad D1-2(2560.862mil,596.671mil) on Top Layer [Top Overlay] to [Top Solder] clearance [4mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (7.795mil < 10mil) Between Track (2475.905mil,2347.559mil)(2475.905mil,2382.992mil) on Top Overlay And Pad X2-2(2425.709mil,2320mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.795mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (7.795mil < 10mil) Between Track (2475.905mil,2257.008mil)(2475.905mil,2292.441mil) on Top Overlay And Pad X2-2(2425.709mil,2320mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.795mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (7.795mil < 10mil) Between Track (2214.095mil,2347.559mil)(2214.095mil,2382.992mil) on Top Overlay And Pad X2-1(2264.291mil,2320mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.795mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (7.795mil < 10mil) Between Track (2214.095mil,2257.008mil)(2214.095mil,2292.441mil) on Top Overlay And Pad X2-1(2264.291mil,2320mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.795mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.997mil < 10mil) Between Track (2664.866mil,2252.535mil)(2664.866mil,2337.465mil) on Top Overlay And Pad X1-2(2635.2mil,2295mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.997mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Track (2505.134mil,2252.535mil)(2664.866mil,2252.535mil) on Top Overlay And Pad X1-2(2635.2mil,2295mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Track (2505.134mil,2337.465mil)(2664.866mil,2337.465mil) on Top Overlay And Pad X1-2(2635.2mil,2295mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.997mil < 10mil) Between Track (2505.134mil,2252.535mil)(2505.134mil,2337.465mil) on Top Overlay And Pad X1-1(2534.8mil,2295mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.997mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Track (2505.134mil,2252.535mil)(2664.866mil,2252.535mil) on Top Overlay And Pad X1-1(2534.8mil,2295mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6mil < 10mil) Between Track (2505.134mil,2337.465mil)(2664.866mil,2337.465mil) on Top Overlay And Pad X1-1(2534.8mil,2295mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.966mil < 10mil) Between Track (1314.225mil,872.43mil)(1314.225mil,1011.91mil) on Top Overlay And Pad U13-1(1302.37mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.966mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (1111.375mil,1011.91mil)(1314.225mil,1011.91mil) on Top Overlay And Pad U13-1(1302.37mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (1111.375mil,1011.91mil)(1314.225mil,1011.91mil) on Top Overlay And Pad U13-2(1276.78mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (1111.375mil,1011.91mil)(1314.225mil,1011.91mil) on Top Overlay And Pad U13-3(1251.19mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (1111.375mil,1011.91mil)(1314.225mil,1011.91mil) on Top Overlay And Pad U13-4(1225.59mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (1111.375mil,1011.91mil)(1314.225mil,1011.91mil) on Top Overlay And Pad U13-5(1200mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (1111.375mil,1011.91mil)(1314.225mil,1011.91mil) on Top Overlay And Pad U13-6(1174.41mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (1111.375mil,1011.91mil)(1314.225mil,1011.91mil) on Top Overlay And Pad U13-7(1148.82mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.966mil < 10mil) Between Track (1111.375mil,872.43mil)(1111.375mil,1011.91mil) on Top Overlay And Pad U13-8(1123.23mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.966mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (1111.375mil,1011.91mil)(1314.225mil,1011.91mil) on Top Overlay And Pad U13-8(1123.23mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.958mil < 10mil) Between Track (1314.225mil,872.43mil)(1314.225mil,1011.91mil) on Top Overlay And Pad U13-16(1302.37mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.958mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (1111.375mil,872.43mil)(1314.225mil,872.43mil) on Top Overlay And Pad U13-16(1302.37mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (1111.375mil,872.43mil)(1314.225mil,872.43mil) on Top Overlay And Pad U13-15(1276.78mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (1111.375mil,872.43mil)(1314.225mil,872.43mil) on Top Overlay And Pad U13-14(1251.19mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (1111.375mil,872.43mil)(1314.225mil,872.43mil) on Top Overlay And Pad U13-13(1225.59mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (1111.375mil,872.43mil)(1314.225mil,872.43mil) on Top Overlay And Pad U13-12(1200mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (1111.375mil,872.43mil)(1314.225mil,872.43mil) on Top Overlay And Pad U13-11(1174.41mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (1111.375mil,872.43mil)(1314.225mil,872.43mil) on Top Overlay And Pad U13-10(1148.82mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.958mil < 10mil) Between Track (1111.375mil,872.43mil)(1111.375mil,1011.91mil) on Top Overlay And Pad U13-9(1123.23mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.958mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (1111.375mil,872.43mil)(1314.225mil,872.43mil) on Top Overlay And Pad U13-9(1123.23mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.966mil < 10mil) Between Track (659.225mil,872.43mil)(659.225mil,1011.91mil) on Top Overlay And Pad U9-1(647.37mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.966mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (456.375mil,1011.91mil)(659.225mil,1011.91mil) on Top Overlay And Pad U9-1(647.37mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (456.375mil,1011.91mil)(659.225mil,1011.91mil) on Top Overlay And Pad U9-2(621.78mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (456.375mil,1011.91mil)(659.225mil,1011.91mil) on Top Overlay And Pad U9-3(596.19mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (456.375mil,1011.91mil)(659.225mil,1011.91mil) on Top Overlay And Pad U9-4(570.59mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (456.375mil,1011.91mil)(659.225mil,1011.91mil) on Top Overlay And Pad U9-5(545mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (456.375mil,1011.91mil)(659.225mil,1011.91mil) on Top Overlay And Pad U9-6(519.41mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (456.375mil,1011.91mil)(659.225mil,1011.91mil) on Top Overlay And Pad U9-7(493.82mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.966mil < 10mil) Between Track (456.375mil,872.43mil)(456.375mil,1011.91mil) on Top Overlay And Pad U9-8(468.23mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.966mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.947mil < 10mil) Between Track (456.375mil,1011.91mil)(659.225mil,1011.91mil) on Top Overlay And Pad U9-8(468.23mil,1055mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.947mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.958mil < 10mil) Between Track (659.225mil,872.43mil)(659.225mil,1011.91mil) on Top Overlay And Pad U9-16(647.37mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.958mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (456.375mil,872.43mil)(659.225mil,872.43mil) on Top Overlay And Pad U9-16(647.37mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (456.375mil,872.43mil)(659.225mil,872.43mil) on Top Overlay And Pad U9-15(621.78mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (456.375mil,872.43mil)(659.225mil,872.43mil) on Top Overlay And Pad U9-14(596.19mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (456.375mil,872.43mil)(659.225mil,872.43mil) on Top Overlay And Pad U9-13(570.59mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (456.375mil,872.43mil)(659.225mil,872.43mil) on Top Overlay And Pad U9-12(545mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (456.375mil,872.43mil)(659.225mil,872.43mil) on Top Overlay And Pad U9-11(519.41mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (456.375mil,872.43mil)(659.225mil,872.43mil) on Top Overlay And Pad U9-10(493.82mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.958mil < 10mil) Between Track (456.375mil,872.43mil)(456.375mil,1011.91mil) on Top Overlay And Pad U9-9(468.23mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.958mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.937mil < 10mil) Between Track (456.375mil,872.43mil)(659.225mil,872.43mil) on Top Overlay And Pad U9-9(468.23mil,829.35mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.937mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.783mil < 10mil) Between Track (247.999mil,1343.5mil)(248.001mil,1398.499mil) on Top Overlay And Pad U8-5(225.405mil,1327.687mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.783mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.595mil < 10mil) Between Track (173.001mil,1335.999mil)(202.999mil,1335.999mil) on Top Overlay And Pad U8-5(225.405mil,1327.687mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.595mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (4.077mil < 10mil) Between Track (133.001mil,1354.368mil)(133.001mil,1387.627mil) on Top Overlay And Pad U8-4(150.595mil,1327.687mil) on Top Layer [Top Overlay] to [Top Solder] clearance [4.077mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.595mil < 10mil) Between Track (173.001mil,1335.999mil)(202.999mil,1335.999mil) on Top Overlay And Pad U8-4(150.595mil,1327.687mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.595mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.795mil < 10mil) Between Track (247.999mil,1343.5mil)(248.001mil,1398.499mil) on Top Overlay And Pad U8-1(225.395mil,1414.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.795mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (4.082mil < 10mil) Between Track (133.001mil,1354.368mil)(133.001mil,1387.627mil) on Top Overlay And Pad U8-3(150.605mil,1414.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [4.082mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.342mil < 10mil) Between Track (1190.26mil,1850.575mil)(1229.63mil,1850.575mil) on Top Overlay And Pad U7-4(1133.855mil,1903mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.342mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.998mil < 10mil) Between Track (1078.794mil,1772.047mil)(1078.794mil,2033.953mil) on Top Overlay And Pad U7-4(1133.855mil,1903mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.998mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3387.254mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-28(1357.89mil,3387mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3387.254mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-27(1377.574mil,3387mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3387.254mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-26(1397.26mil,3387mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3387.254mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-25(1416.944mil,3387mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3387.254mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-24(1436.63mil,3387mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3387.254mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-23(1456.314mil,3387mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3387.254mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-22(1476mil,3387mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1514.898mil,3190.404mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-21(1515mil,3348.11mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1514.898mil,3190.404mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-20(1515mil,3328.424mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1514.898mil,3190.404mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-19(1515mil,3308.74mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1514.898mil,3190.404mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-18(1515mil,3289.054mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1514.898mil,3190.404mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-17(1515mil,3269.37mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1514.898mil,3190.404mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-16(1515mil,3249.684mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1514.898mil,3190.404mil)(1514.898mil,3387.254mil) on Top Overlay And Pad U4-15(1515mil,3230mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1514.898mil,3190.404mil) on Top Overlay And Pad U4-14(1475.11mil,3191mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1514.898mil,3190.404mil) on Top Overlay And Pad U4-13(1455.424mil,3191mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1514.898mil,3190.404mil) on Top Overlay And Pad U4-12(1435.74mil,3191mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1514.898mil,3190.404mil) on Top Overlay And Pad U4-11(1416.054mil,3191mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1514.898mil,3190.404mil) on Top Overlay And Pad U4-10(1396.37mil,3191mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1514.898mil,3190.404mil) on Top Overlay And Pad U4-9(1376.684mil,3191mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1514.898mil,3190.404mil) on Top Overlay And Pad U4-8(1357mil,3191mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1318.046mil,3387.254mil) on Top Overlay And Pad U4-7(1318mil,3229.89mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1318.046mil,3387.254mil) on Top Overlay And Pad U4-6(1318mil,3249.574mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1318.046mil,3387.254mil) on Top Overlay And Pad U4-5(1318mil,3269.26mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1318.046mil,3387.254mil) on Top Overlay And Pad U4-4(1318mil,3288.944mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1318.046mil,3387.254mil) on Top Overlay And Pad U4-3(1318mil,3308.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1318.046mil,3387.254mil) on Top Overlay And Pad U4-2(1318mil,3328.314mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (1318.046mil,3190.404mil)(1318.046mil,3387.254mil) on Top Overlay And Pad U4-1(1318mil,3348mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.985mil < 10mil) Between Track (2466.849mil,2002.646mil)(2466.85mil,2002.646mil) on Top Overlay And Pad U3-64(2496.37mil,1987.64mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.985mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.985mil < 10mil) Between Track (2466.85mil,2002.646mil)(2466.85mil,2036.85mil) on Top Overlay And Pad U3-64(2496.37mil,1987.64mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.985mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (8.985mil < 10mil) Between Region (0 hole(s)) Top Overlay And Pad U3-64(2496.37mil,1987.64mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.985mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.985mil < 10mil) Between Track (2432.645mil,2036.85mil)(2466.849mil,2002.646mil) on Top Overlay And Pad U3-64(2496.37mil,1987.64mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.985mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.984mil < 10mil) Between Track (2466.85mil,1643.15mil)(2466.85mil,1677.355mil) on Top Overlay And Pad U3-49(2496.37mil,1692.36mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.984mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.984mil < 10mil) Between Track (2432.645mil,1643.15mil)(2466.85mil,1643.15mil) on Top Overlay And Pad U3-48(2417.64mil,1613.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.984mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.985mil < 10mil) Between Track (2073.15mil,1643.15mil)(2107.354mil,1643.15mil) on Top Overlay And Pad U3-33(2122.36mil,1613.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.985mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.984mil < 10mil) Between Track (2073.15mil,1643.15mil)(2073.15mil,1677.355mil) on Top Overlay And Pad U3-32(2043.63mil,1692.36mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.984mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.985mil < 10mil) Between Track (2073.15mil,2002.646mil)(2073.15mil,2036.85mil) on Top Overlay And Pad U3-17(2043.63mil,1987.64mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.985mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.984mil < 10mil) Between Track (2073.15mil,2036.85mil)(2107.355mil,2036.85mil) on Top Overlay And Pad U3-16(2122.36mil,2066.37mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.984mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (8.985mil < 10mil) Between Region (0 hole(s)) Top Overlay And Pad U3-1(2417.64mil,2066.37mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.985mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.984mil < 10mil) Between Track (2432.645mil,2036.85mil)(2466.85mil,2036.85mil) on Top Overlay And Pad U3-1(2417.64mil,2066.37mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.984mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (3.984mil < 10mil) Between Track (2432.645mil,2036.85mil)(2466.849mil,2002.646mil) on Top Overlay And Pad U3-1(2417.64mil,2066.37mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.984mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.907mil < 10mil) Between Track (3641.724mil,3279.899mil)(3988.276mil,3279.899mil) on Top Overlay And Pad U2-1(3965mil,3329.022mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.907mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.907mil < 10mil) Between Track (3641.724mil,3279.899mil)(3988.276mil,3279.899mil) on Top Overlay And Pad U2-2(3915mil,3329.022mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.907mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.907mil < 10mil) Between Track (3641.724mil,3279.899mil)(3988.276mil,3279.899mil) on Top Overlay And Pad U2-3(3865mil,3329.022mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.907mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.907mil < 10mil) Between Track (3641.724mil,3279.899mil)(3988.276mil,3279.899mil) on Top Overlay And Pad U2-4(3815mil,3329.022mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.907mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.907mil < 10mil) Between Track (3641.724mil,3279.899mil)(3988.276mil,3279.899mil) on Top Overlay And Pad U2-5(3765mil,3329.022mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.907mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.907mil < 10mil) Between Track (3641.724mil,3279.899mil)(3988.276mil,3279.899mil) on Top Overlay And Pad U2-6(3715mil,3329.022mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.907mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.907mil < 10mil) Between Track (3641.724mil,3279.899mil)(3988.276mil,3279.899mil) on Top Overlay And Pad U2-7(3665mil,3329.022mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.907mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.905mil < 10mil) Between Track (3641.724mil,3160.103mil)(3988.276mil,3160.103mil) on Top Overlay And Pad U2-14(3965mil,3110.982mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.905mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.905mil < 10mil) Between Track (3641.724mil,3160.103mil)(3988.276mil,3160.103mil) on Top Overlay And Pad U2-13(3915mil,3110.982mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.905mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.905mil < 10mil) Between Track (3641.724mil,3160.103mil)(3988.276mil,3160.103mil) on Top Overlay And Pad U2-12(3865mil,3110.982mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.905mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.905mil < 10mil) Between Track (3641.724mil,3160.103mil)(3988.276mil,3160.103mil) on Top Overlay And Pad U2-11(3815mil,3110.982mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.905mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.905mil < 10mil) Between Track (3641.724mil,3160.103mil)(3988.276mil,3160.103mil) on Top Overlay And Pad U2-10(3765mil,3110.982mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.905mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.905mil < 10mil) Between Track (3641.724mil,3160.103mil)(3988.276mil,3160.103mil) on Top Overlay And Pad U2-9(3715mil,3110.982mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.905mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.905mil < 10mil) Between Track (3641.724mil,3160.103mil)(3988.276mil,3160.103mil) on Top Overlay And Pad U2-8(3665mil,3110.982mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.905mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1171mil,1328.001mil)(1171mil,1342.001mil) on Top Overlay And Pad R66-1(1185mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1199mil,1328.001mil)(1199mil,1342.001mil) on Top Overlay And Pad R66-1(1185mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1171mil,1328.001mil)(1171mil,1342.001mil) on Top Overlay And Pad R66-2(1185mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1199mil,1328.001mil)(1199mil,1342.001mil) on Top Overlay And Pad R66-2(1185mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1226mil,1328.001mil)(1226mil,1342.001mil) on Top Overlay And Pad R63-1(1240mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1254mil,1328.001mil)(1254mil,1342.001mil) on Top Overlay And Pad R63-1(1240mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1226mil,1328.001mil)(1226mil,1342.001mil) on Top Overlay And Pad R63-2(1240mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1254mil,1328.001mil)(1254mil,1342.001mil) on Top Overlay And Pad R63-2(1240mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1281mil,1328.001mil)(1281mil,1342.001mil) on Top Overlay And Pad R62-1(1295mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1309mil,1328.001mil)(1309mil,1342.001mil) on Top Overlay And Pad R62-1(1295mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1281mil,1328.001mil)(1281mil,1342.001mil) on Top Overlay And Pad R62-2(1295mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1309mil,1328.001mil)(1309mil,1342.001mil) on Top Overlay And Pad R62-2(1295mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1116mil,1328.001mil)(1116mil,1342.001mil) on Top Overlay And Pad R61-1(1130mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1144mil,1328.001mil)(1144mil,1342.001mil) on Top Overlay And Pad R61-1(1130mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1116mil,1328.001mil)(1116mil,1342.001mil) on Top Overlay And Pad R61-2(1130mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1144mil,1328.001mil)(1144mil,1342.001mil) on Top Overlay And Pad R61-2(1130mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1124.39mil,595.826mil)(1124.39mil,609.826mil) on Top Overlay And Pad R60-1(1138.39mil,635.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1152.39mil,595.826mil)(1152.39mil,609.826mil) on Top Overlay And Pad R60-1(1138.39mil,635.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1124.39mil,595.826mil)(1124.39mil,609.826mil) on Top Overlay And Pad R60-2(1138.39mil,569.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1152.39mil,595.826mil)(1152.39mil,609.826mil) on Top Overlay And Pad R60-2(1138.39mil,569.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1061mil,1328.001mil)(1061mil,1342.001mil) on Top Overlay And Pad R59-1(1075mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1089mil,1328.001mil)(1089mil,1342.001mil) on Top Overlay And Pad R59-1(1075mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1061mil,1328.001mil)(1061mil,1342.001mil) on Top Overlay And Pad R59-2(1075mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1089mil,1328.001mil)(1089mil,1342.001mil) on Top Overlay And Pad R59-2(1075mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1179.39mil,595.826mil)(1179.39mil,609.826mil) on Top Overlay And Pad R58-1(1193.39mil,635.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1207.39mil,595.826mil)(1207.39mil,609.826mil) on Top Overlay And Pad R58-1(1193.39mil,635.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1179.39mil,595.826mil)(1179.39mil,609.826mil) on Top Overlay And Pad R58-2(1193.39mil,569.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1207.39mil,595.826mil)(1207.39mil,609.826mil) on Top Overlay And Pad R58-2(1193.39mil,569.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3345.001mil,1770mil)(3359.001mil,1770mil) on Top Overlay And Pad R67-1(3385.001mil,1756mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3345.001mil,1742mil)(3359.001mil,1742mil) on Top Overlay And Pad R67-1(3385.001mil,1756mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3345.001mil,1770mil)(3359.001mil,1770mil) on Top Overlay And Pad R67-2(3319.001mil,1756mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3345.001mil,1742mil)(3359.001mil,1742mil) on Top Overlay And Pad R67-2(3319.001mil,1756mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (934.39mil,966.824mil)(948.39mil,966.824mil) on Top Overlay And Pad R52-1(908.39mil,980.824mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (934.39mil,994.824mil)(948.39mil,994.824mil) on Top Overlay And Pad R52-1(908.39mil,980.824mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (934.39mil,966.824mil)(948.39mil,966.824mil) on Top Overlay And Pad R52-2(974.39mil,980.824mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (934.39mil,994.824mil)(948.39mil,994.824mil) on Top Overlay And Pad R52-2(974.39mil,980.824mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (936.389mil,896.825mil)(950.389mil,896.825mil) on Top Overlay And Pad R51-1(910.389mil,910.825mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (936.389mil,924.825mil)(950.389mil,924.825mil) on Top Overlay And Pad R51-1(910.389mil,910.825mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (936.389mil,896.825mil)(950.389mil,896.825mil) on Top Overlay And Pad R51-2(976.389mil,910.825mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (936.389mil,924.825mil)(950.389mil,924.825mil) on Top Overlay And Pad R51-2(976.389mil,910.825mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3222mil,815mil)(3222mil,829mil) on Top Overlay And Pad R57-1(3236mil,855mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3250mil,815mil)(3250mil,829mil) on Top Overlay And Pad R57-1(3236mil,855mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.294mil < 10mil) Between Text "R57" (3256mil,889mil) on Top Overlay And Pad R57-1(3236mil,855mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.294mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3222mil,815mil)(3222mil,829mil) on Top Overlay And Pad R57-2(3236mil,789mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3250mil,815mil)(3250mil,829mil) on Top Overlay And Pad R57-2(3236mil,789mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (826mil,938.001mil)(826mil,952.001mil) on Top Overlay And Pad R48-1(840mil,978.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (854mil,938.001mil)(854mil,952.001mil) on Top Overlay And Pad R48-1(840mil,978.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (826mil,938.001mil)(826mil,952.001mil) on Top Overlay And Pad R48-2(840mil,912.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (854mil,938.001mil)(854mil,952.001mil) on Top Overlay And Pad R48-2(840mil,912.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3279mil,814mil)(3279mil,828mil) on Top Overlay And Pad R55-1(3293mil,854mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3307mil,814mil)(3307mil,828mil) on Top Overlay And Pad R55-1(3293mil,854mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3279mil,814mil)(3279mil,828mil) on Top Overlay And Pad R55-2(3293mil,788mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3307mil,814mil)(3307mil,828mil) on Top Overlay And Pad R55-2(3293mil,788mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3280.001mil,578mil)(3294.001mil,578mil) on Top Overlay And Pad R53-1(3320.001mil,564mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3280.001mil,550mil)(3294.001mil,550mil) on Top Overlay And Pad R53-1(3320.001mil,564mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3280.001mil,578mil)(3294.001mil,578mil) on Top Overlay And Pad R53-2(3254.001mil,564mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (3280.001mil,550mil)(3294.001mil,550mil) on Top Overlay And Pad R53-2(3254.001mil,564mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.5mil < 10mil) Between Track (3943mil,683mil)(3943mil,713mil) on Top Overlay And Pad R49-1(3968mil,752mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.5mil < 10mil) Between Track (3993mil,683mil)(3993mil,713mil) on Top Overlay And Pad R49-1(3968mil,752mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.5mil < 10mil) Between Track (3943mil,683mil)(3943mil,713mil) on Top Overlay And Pad R49-2(3968mil,644mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.5mil < 10mil) Between Track (3993mil,683mil)(3993mil,713mil) on Top Overlay And Pad R49-2(3968mil,644mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (516mil,1328.001mil)(516mil,1342.001mil) on Top Overlay And Pad R41-1(530mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (544mil,1328.001mil)(544mil,1342.001mil) on Top Overlay And Pad R41-1(530mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (516mil,1328.001mil)(516mil,1342.001mil) on Top Overlay And Pad R41-2(530mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (544mil,1328.001mil)(544mil,1342.001mil) on Top Overlay And Pad R41-2(530mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (571mil,1328.001mil)(571mil,1342.001mil) on Top Overlay And Pad R40-1(585mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (599mil,1328.001mil)(599mil,1342.001mil) on Top Overlay And Pad R40-1(585mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (571mil,1328.001mil)(571mil,1342.001mil) on Top Overlay And Pad R40-2(585mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (599mil,1328.001mil)(599mil,1342.001mil) on Top Overlay And Pad R40-2(585mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (626mil,1328.001mil)(626mil,1342.001mil) on Top Overlay And Pad R39-1(640mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (654mil,1328.001mil)(654mil,1342.001mil) on Top Overlay And Pad R39-1(640mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (626mil,1328.001mil)(626mil,1342.001mil) on Top Overlay And Pad R39-2(640mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (654mil,1328.001mil)(654mil,1342.001mil) on Top Overlay And Pad R39-2(640mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (461mil,1328.001mil)(461mil,1342.001mil) on Top Overlay And Pad R38-1(475mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (489mil,1328.001mil)(489mil,1342.001mil) on Top Overlay And Pad R38-1(475mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (461mil,1328.001mil)(461mil,1342.001mil) on Top Overlay And Pad R38-2(475mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (489mil,1328.001mil)(489mil,1342.001mil) on Top Overlay And Pad R38-2(475mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (469.39mil,595.826mil)(469.39mil,609.826mil) on Top Overlay And Pad R37-1(483.39mil,635.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (497.39mil,595.826mil)(497.39mil,609.826mil) on Top Overlay And Pad R37-1(483.39mil,635.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (469.39mil,595.826mil)(469.39mil,609.826mil) on Top Overlay And Pad R37-2(483.39mil,569.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (497.39mil,595.826mil)(497.39mil,609.826mil) on Top Overlay And Pad R37-2(483.39mil,569.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (406mil,1328.001mil)(406mil,1342.001mil) on Top Overlay And Pad R36-1(420mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (434mil,1328.001mil)(434mil,1342.001mil) on Top Overlay And Pad R36-1(420mil,1368.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (406mil,1328.001mil)(406mil,1342.001mil) on Top Overlay And Pad R36-2(420mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (434mil,1328.001mil)(434mil,1342.001mil) on Top Overlay And Pad R36-2(420mil,1302.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (524.39mil,595.826mil)(524.39mil,609.826mil) on Top Overlay And Pad R35-1(538.39mil,635.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (552.39mil,595.826mil)(552.39mil,609.826mil) on Top Overlay And Pad R35-1(538.39mil,635.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (524.39mil,595.826mil)(524.39mil,609.826mil) on Top Overlay And Pad R35-2(538.39mil,569.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (552.39mil,595.826mil)(552.39mil,609.826mil) on Top Overlay And Pad R35-2(538.39mil,569.826mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (4913mil,3293.999mil)(4913mil,3307.999mil) on Top Overlay And Pad R34-1(4899mil,3267.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (4885mil,3293.999mil)(4885mil,3307.999mil) on Top Overlay And Pad R34-1(4899mil,3267.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (4913mil,3293.999mil)(4913mil,3307.999mil) on Top Overlay And Pad R34-2(4899mil,3333.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (4885mil,3293.999mil)(4885mil,3307.999mil) on Top Overlay And Pad R34-2(4899mil,3333.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (7.295mil < 10mil) Between Text "R34" (4915mil,3366mil) on Top Overlay And Pad R34-2(4899mil,3333.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.295mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (4825mil,3293.999mil)(4825mil,3307.999mil) on Top Overlay And Pad R31-1(4839mil,3267.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (4853mil,3293.999mil)(4853mil,3307.999mil) on Top Overlay And Pad R31-1(4839mil,3267.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (4825mil,3293.999mil)(4825mil,3307.999mil) on Top Overlay And Pad R31-2(4839mil,3333.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (4853mil,3293.999mil)(4853mil,3307.999mil) on Top Overlay And Pad R31-2(4839mil,3333.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (279.39mil,966.824mil)(293.39mil,966.824mil) on Top Overlay And Pad R33-1(253.39mil,980.824mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (279.39mil,994.824mil)(293.39mil,994.824mil) on Top Overlay And Pad R33-1(253.39mil,980.824mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (279.39mil,966.824mil)(293.39mil,966.824mil) on Top Overlay And Pad R33-2(319.39mil,980.824mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (279.39mil,994.824mil)(293.39mil,994.824mil) on Top Overlay And Pad R33-2(319.39mil,980.824mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (281.389mil,896.825mil)(295.389mil,896.825mil) on Top Overlay And Pad R32-1(255.389mil,910.825mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (281.389mil,924.825mil)(295.389mil,924.825mil) on Top Overlay And Pad R32-1(255.389mil,910.825mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (281.389mil,896.825mil)(295.389mil,896.825mil) on Top Overlay And Pad R32-2(321.389mil,910.825mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (281.389mil,924.825mil)(295.389mil,924.825mil) on Top Overlay And Pad R32-2(321.389mil,910.825mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (171mil,938.001mil)(171mil,952.001mil) on Top Overlay And Pad R30-1(185mil,978.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (199mil,938.001mil)(199mil,952.001mil) on Top Overlay And Pad R30-1(185mil,978.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (171mil,938.001mil)(171mil,952.001mil) on Top Overlay And Pad R30-2(185mil,912.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (199mil,938.001mil)(199mil,952.001mil) on Top Overlay And Pad R30-2(185mil,912.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (180.999mil,1507mil)(194.999mil,1507mil) on Top Overlay And Pad R29-1(154.999mil,1493mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (180.999mil,1479mil)(194.999mil,1479mil) on Top Overlay And Pad R29-1(154.999mil,1493mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (6.648mil < 10mil) Between Text "R29" (25mil,1470mil) on Top Overlay And Pad R29-1(154.999mil,1493mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.648mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (180.999mil,1507mil)(194.999mil,1507mil) on Top Overlay And Pad R29-2(220.999mil,1493mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (180.999mil,1479mil)(194.999mil,1479mil) on Top Overlay And Pad R29-2(220.999mil,1493mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (398.956mil,2411.001mil)(412.956mil,2411.001mil) on Top Overlay And Pad R27-1(438.956mil,2397.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (398.956mil,2383.001mil)(412.956mil,2383.001mil) on Top Overlay And Pad R27-1(438.956mil,2397.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (398.956mil,2411.001mil)(412.956mil,2411.001mil) on Top Overlay And Pad R27-2(372.956mil,2397.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (398.956mil,2383.001mil)(412.956mil,2383.001mil) on Top Overlay And Pad R27-2(372.956mil,2397.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (8.604mil < 10mil) Between Text "R27" (241mil,2372mil) on Top Overlay And Pad R27-2(372.956mil,2397.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.604mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (398.954mil,2483.001mil)(412.954mil,2483.001mil) on Top Overlay And Pad R26-1(372.954mil,2497.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (398.954mil,2511.001mil)(412.954mil,2511.001mil) on Top Overlay And Pad R26-1(372.954mil,2497.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (8.648mil < 10mil) Between Text "R26" (240.955mil,2477.001mil) on Top Overlay And Pad R26-1(372.954mil,2497.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.648mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (398.954mil,2483.001mil)(412.954mil,2483.001mil) on Top Overlay And Pad R26-2(438.954mil,2497.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (398.954mil,2511.001mil)(412.954mil,2511.001mil) on Top Overlay And Pad R26-2(438.954mil,2497.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1714mil,3222.999mil)(1714mil,3236.999mil) on Top Overlay And Pad R17-1(1700mil,3196.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1686mil,3222.999mil)(1686mil,3236.999mil) on Top Overlay And Pad R17-1(1700mil,3196.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1714mil,3222.999mil)(1714mil,3236.999mil) on Top Overlay And Pad R17-2(1700mil,3262.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1686mil,3222.999mil)(1686mil,3236.999mil) on Top Overlay And Pad R17-2(1700mil,3262.999mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.5mil < 10mil) Between Track (1305mil,3530mil)(1305mil,3560mil) on Top Overlay And Pad R16-2(1330mil,3491mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.5mil < 10mil) Between Track (1355mil,3530mil)(1355mil,3560mil) on Top Overlay And Pad R16-2(1330mil,3491mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.294mil < 10mil) Between Text "R16" (1283mil,3499mil) on Top Overlay And Pad R16-2(1330mil,3491mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.294mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.5mil < 10mil) Between Track (1305mil,3530mil)(1305mil,3560mil) on Top Overlay And Pad R16-1(1330mil,3599mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.5mil < 10mil) Between Track (1355mil,3530mil)(1355mil,3560mil) on Top Overlay And Pad R16-1(1330mil,3599mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.294mil < 10mil) Between Text "R16" (1283mil,3499mil) on Top Overlay And Pad R16-1(1330mil,3599mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.294mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1630mil,3222.001mil)(1630mil,3236.001mil) on Top Overlay And Pad R15-1(1644mil,3262.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1658mil,3222.001mil)(1658mil,3236.001mil) on Top Overlay And Pad R15-1(1644mil,3262.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (9.293mil < 10mil) Between Text "R15" (1658mil,3296mil) on Top Overlay And Pad R15-1(1644mil,3262.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.293mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1630mil,3222.001mil)(1630mil,3236.001mil) on Top Overlay And Pad R15-2(1644mil,3196.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1658mil,3222.001mil)(1658mil,3236.001mil) on Top Overlay And Pad R15-2(1644mil,3196.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.5mil < 10mil) Between Track (1530mil,3529mil)(1530mil,3559mil) on Top Overlay And Pad R14-2(1505mil,3490mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.5mil < 10mil) Between Track (1480mil,3529mil)(1480mil,3559mil) on Top Overlay And Pad R14-2(1505mil,3490mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.5mil < 10mil) Between Track (1530mil,3529mil)(1530mil,3559mil) on Top Overlay And Pad R14-1(1505mil,3598mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (5.5mil < 10mil) Between Track (1480mil,3529mil)(1480mil,3559mil) on Top Overlay And Pad R14-1(1505mil,3598mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.5mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1181mil,3315mil)(1195mil,3315mil) on Top Overlay And Pad R13-1(1221mil,3329mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1181mil,3343mil)(1195mil,3343mil) on Top Overlay And Pad R13-1(1221mil,3329mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1181mil,3315mil)(1195mil,3315mil) on Top Overlay And Pad R13-2(1155mil,3329mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1181mil,3343mil)(1195mil,3343mil) on Top Overlay And Pad R13-2(1155mil,3329mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1990.999mil,2354mil)(2004.999mil,2354mil) on Top Overlay And Pad R11-1(1964.999mil,2368mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1990.999mil,2382mil)(2004.999mil,2382mil) on Top Overlay And Pad R11-1(1964.999mil,2368mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1990.999mil,2354mil)(2004.999mil,2354mil) on Top Overlay And Pad R11-2(2030.999mil,2368mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1990.999mil,2382mil)(2004.999mil,2382mil) on Top Overlay And Pad R11-2(2030.999mil,2368mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2608.001mil,1939mil)(2622.001mil,1939mil) on Top Overlay And Pad R10-1(2648.001mil,1925mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
|
|||
|
|
Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2608.001mil,1911mil)(2622.001mil,1911mil) on Top Overlay And Pad R10-1(2648.001mil,1925mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
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Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2608.001mil,1939mil)(2622.001mil,1939mil) on Top Overlay And Pad R10-2(2582.001mil,1925mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
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Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (2608.001mil,1911mil)(2622.001mil,1911mil) on Top Overlay And Pad R10-2(2582.001mil,1925mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
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Violation between Silk To Solder Mask Clearance Constraint: (2mil < 10mil) Between Track (1847.999mil,1768mil)(1861.999mil,1768mil) on Top Overlay And Pad R9-1(1821.999mil,1782mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2mil]
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Rule Violations :367
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Processing Rule : Silk to Silk (Clearance=10mil) (All),(All)
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Violation between Silk To Silk Clearance Constraint: (9.828mil < 10mil) Between Text "U5" (412mil,2751mil) on Top Overlay And Arc (488.699mil,2732.345mil) on Top Overlay Silk Text to Silk Clearance [9.828mil]
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Violation between Silk To Silk Clearance Constraint: (6.351mil < 10mil) Between Text "R13" (1020mil,3314mil) on Top Overlay And Arc (1116mil,3486mil) on Top Overlay Silk Text to Silk Clearance [6.351mil]
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Violation between Silk To Silk Clearance Constraint: (6.933mil < 10mil) Between Text "U4" (1235mil,3375mil) on Top Overlay And Arc (1116mil,3486mil) on Top Overlay Silk Text to Silk Clearance [6.933mil]
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Violation between Silk To Silk Clearance Constraint: (Collision < 10mil) Between Text "R16" (1283mil,3499mil) on Top Overlay And Arc (1116mil,3486mil) on Top Overlay Silk Text to Silk Clearance [0mil]
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Violation between Silk To Silk Clearance Constraint: (Collision < 10mil) Between Text "+" (1076mil,3406mil) on Top Overlay And Arc (1116mil,3486mil) on Top Overlay Silk Text to Silk Clearance [0mil]
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Violation between Silk To Silk Clearance Constraint: (1.202mil < 10mil) Between Text "R13" (1020mil,3314mil) on Top Overlay And Arc (1116mil,3486mil) on Top Overlay Silk Text to Silk Clearance [1.202mil]
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Violation between Silk To Silk Clearance Constraint: (Collision < 10mil) Between Text "+" (1076mil,3406mil) on Top Overlay And Arc (1116mil,3486mil) on Top Overlay Silk Text to Silk Clearance [0mil]
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Violation between Silk To Silk Clearance Constraint: (1.202mil < 10mil) Between Text "R13" (1020mil,3314mil) on Top Overlay And Arc (1116mil,3486mil) on Top Overlay Silk Text to Silk Clearance [1.202mil]
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Violation between Silk To Silk Clearance Constraint: (6.933mil < 10mil) Between Text "U4" (1235mil,3375mil) on Top Overlay And Arc (1116mil,3486mil) on Top Overlay Silk Text to Silk Clearance [6.933mil]
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Violation between Silk To Silk Clearance Constraint: (Collision < 10mil) Between Text "R16" (1283mil,3499mil) on Top Overlay And Arc (1116mil,3486mil) on Top Overlay Silk Text to Silk Clearance [0mil]
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Violation between Silk To Silk Clearance Constraint: (6.239mil < 10mil) Between Text "3V3" (3109mil,2129mil) on Top Overlay And Arc (3193mil,2070mil) on Top Overlay Silk Text to Silk Clearance [6.239mil]
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Rule Violations :11
|
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Processing Rule : Net Antennae (Tolerance=0mil) (All)
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Rule Violations :0
|
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Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
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Rule Violations :0
|
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Processing Rule : Clearance Constraint (Gap=15mil) (InPolygon),(All)
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Rule Violations :0
|
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Violations Detected : 500
|
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Time Elapsed : 00:00:01
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