201 lines
6.3 KiB
C
201 lines
6.3 KiB
C
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/* -----------------------------------------------------------------------------
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* Copyright (c) 2013-2017 ARM Ltd.
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*
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* This software is provided 'as-is', without any express or implied warranty.
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* In no event will the authors be held liable for any damages arising from
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* the use of this software. Permission is granted to anyone to use this
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* software for any purpose, including commercial applications, and to alter
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* it and redistribute it freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software in
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* a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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*
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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*
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*
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* $Date: 19. September 2017
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* $Revision: V2.3
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*
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* Project: OTG Full/Low-Speed Common Driver for ST STM32F1xx
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* -------------------------------------------------------------------------- */
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/* History:
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* Version 2.3
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* Removed unnecessary include of cmsis_os.h
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* Version 2.2
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* Corrected over-current pin configuration
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* Version 2.1
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* Added configuration for USB Device VBUS pin so connection/disconnection of
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* USB cable can be detected when device is self-powered
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* Version 2.0
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* Based on API V2.01
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* Version 1.03
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* Based on API V1.10 (namespace prefix ARM_ added)
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* Version 1.00
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* Initial release
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*/
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#include <stdint.h>
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#include <string.h>
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#include "stm32f10x.h"
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#include "GPIO_STM32F10x.h"
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#include "OTG_STM32F10x_cl.h"
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#include "Driver_USBH.h"
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#include "Driver_USBD.h"
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extern void USBH_FS_IRQ (uint32_t gintsts);
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extern void USBD_FS_IRQ (uint32_t gintsts);
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uint8_t otg_fs_role = ARM_USB_ROLE_NONE;
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// Common IRQ Routine **********************************************************
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/**
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\fn void OTG_FS_IRQHandler (void)
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\brief USB Interrupt Routine (IRQ).
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*/
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void OTG_FS_IRQHandler (void) {
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uint32_t gintsts;
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gintsts = OTG_FS->GINTSTS & OTG_FS->GINTMSK;
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#if (defined(MX_USB_OTG_FS_HOST) && defined(MX_USB_OTG_FS_DEVICE))
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switch (otg_fs_role) {
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#ifdef MX_USB_OTG_FS_HOST
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case ARM_USB_ROLE_HOST:
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USBH_FS_IRQ (gintsts);
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break;
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#endif
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#ifdef MX_USB_OTG_FS_DEVICE
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case ARM_USB_ROLE_DEVICE:
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USBD_FS_IRQ (gintsts);
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break;
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#endif
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default:
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break;
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}
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#else
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#ifdef MX_USB_OTG_FS_HOST
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USBH_FS_IRQ (gintsts);
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#else
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USBD_FS_IRQ (gintsts);
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#endif
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#endif
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}
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// Public Functions ************************************************************
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/**
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\fn void OTG_FS_PinsConfigure (uint8_t pins_mask)
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\brief Configure single or multiple USB Pin(s).
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\param[in] Mask of pins to be configured (possible masking values:
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USB_PIN_DP, USB_PIN_DM, USB_PIN_VBUS, USB_PIN_OC, USB_PIN_ID)
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*/
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void OTG_FS_PinsConfigure (uint8_t pins_mask) {
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#ifdef MX_USB_OTG_FS_VBUS_Power_Pin // Host VBUS power driving pin (output)
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if ((pins_mask & ARM_USB_PIN_VBUS) != 0U) {
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if (otg_fs_role == ARM_USB_ROLE_DEVICE) {
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GPIO_PortClock (GPIOA, true);
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GPIO_PinConfigure(GPIOA, 9, GPIO_IN_FLOATING, GPIO_MODE_INPUT);
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}
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if (otg_fs_role == ARM_USB_ROLE_HOST) {
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GPIO_PortClock (MX_USB_OTG_FS_VBUS_Power_GPIOx, true);
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#if (USB_OTG_FS_VBUS_Power_Pin_Active == 0)
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GPIO_PinWrite (MX_USB_OTG_FS_VBUS_Power_GPIOx, MX_USB_OTG_FS_VBUS_Power_GPIO_Pin, 1U);
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#else
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GPIO_PinWrite (MX_USB_OTG_FS_VBUS_Power_GPIOx, MX_USB_OTG_FS_VBUS_Power_GPIO_Pin, 0U);
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#endif
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GPIO_PinConfigure(MX_USB_OTG_FS_VBUS_Power_GPIOx, MX_USB_OTG_FS_VBUS_Power_GPIO_Pin, GPIO_OUT_PUSH_PULL, GPIO_MODE_OUT10MHZ);
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}
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}
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#endif
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#ifdef MX_USB_OTG_FS_Overcurrent_Pin // Host overcurrent sensing pin (input)
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if ((pins_mask & ARM_USB_PIN_OC) != 0U) {
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if (otg_fs_role == ARM_USB_ROLE_HOST) {
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GPIO_PortClock (MX_USB_OTG_FS_Overcurrent_GPIOx, true);
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GPIO_PinConfigure(MX_USB_OTG_FS_Overcurrent_GPIOx, MX_USB_OTG_FS_Overcurrent_GPIO_Pin, GPIO_IN_FLOATING, GPIO_MODE_INPUT);
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}
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}
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#endif
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}
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/**
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\fn void OTG_FS_PinsUnconfigure (uint8_t pins_mask)
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\brief Unconfigure to reset settings single or multiple USB Pin(s).
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\param[in] Mask of pins to be unconfigured (possible masking values:
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USB_PIN_DP, USB_PIN_DM, USB_PIN_VBUS, USB_PIN_OC, USB_PIN_ID)
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*/
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void OTG_FS_PinsUnconfigure (uint8_t pins_mask) {
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#ifdef MX_USB_OTG_FS_VBUS_Power_Pin
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if ((pins_mask & ARM_USB_PIN_VBUS) != 0U) {
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if (otg_fs_role == ARM_USB_ROLE_HOST) {
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GPIO_PortClock (MX_USB_OTG_FS_VBUS_Power_GPIOx, true);
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GPIO_PinConfigure(MX_USB_OTG_FS_VBUS_Power_GPIOx, MX_USB_OTG_FS_VBUS_Power_GPIO_Pin, GPIO_IN_FLOATING, GPIO_MODE_INPUT);
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}
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}
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#endif
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#ifdef MX_USB_OTG_FS_Overcurrent_Pin
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if ((pins_mask & ARM_USB_PIN_OC) != 0U) {
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if (otg_fs_role == ARM_USB_ROLE_HOST) {
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GPIO_PortClock (MX_USB_OTG_FS_Overcurrent_GPIOx, true);
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GPIO_PinConfigure(MX_USB_OTG_FS_Overcurrent_GPIOx, MX_USB_OTG_FS_Overcurrent_GPIO_Pin, GPIO_IN_FLOATING, GPIO_MODE_INPUT);
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}
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}
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#endif
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}
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/**
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\fn void OTG_FS_PinVbusOnOff (bool state)
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\brief Drive VBUS Pin On/Off.
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\param[in] state State On/Off (true = On, false = Off)
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*/
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void OTG_FS_PinVbusOnOff (bool state) {
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#ifdef MX_USB_OTG_FS_VBUS_Power_Pin
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if (otg_fs_role == ARM_USB_ROLE_HOST) {
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#if (USB_OTG_FS_VBUS_Power_Pin_Active == 0)
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GPIO_PinWrite (MX_USB_OTG_FS_VBUS_Power_GPIOx, MX_USB_OTG_FS_VBUS_Power_GPIO_Pin,((state == true) ? 0U : 1U));
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#else
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GPIO_PinWrite (MX_USB_OTG_FS_VBUS_Power_GPIOx, MX_USB_OTG_FS_VBUS_Power_GPIO_Pin,((state == true) ? 1U : 0U));
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#endif
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}
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#endif
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}
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/**
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\fn bool OTG_FS_PinGetOC (void)
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\brief Get state of Overcurrent Pin.
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\return overcurrent state (true = Overcurrent active, false = No overcurrent)
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*/
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bool OTG_FS_PinGetOC (void) {
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#ifdef MX_USB_OTG_FS_Overcurrent_Pin
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if (otg_fs_role == ARM_USB_ROLE_HOST) {
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#if (USB_OTG_FS_Overcurrent_Pin_Active == 0)
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return ((GPIO_PinRead (MX_USB_OTG_FS_Overcurrent_GPIOx, MX_USB_OTG_FS_Overcurrent_GPIO_Pin) == 0U) ? true : false);
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#else
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return ((GPIO_PinRead (MX_USB_OTG_FS_Overcurrent_GPIOx, MX_USB_OTG_FS_Overcurrent_GPIO_Pin) == 1U) ? true : false);
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#endif
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}
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return false;
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#else
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return false;
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#endif
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}
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