473 lines
13 KiB
C
473 lines
13 KiB
C
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/* ----------------------------------------------------------------------
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* Copyright (C) 2015 ARM Limited. All rights reserved.
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*
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* $Date: 27. August 2013
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* $Revision: V1.2
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*
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* Project: DMA Driver for ST STM32F10x
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* -------------------------------------------------------------------- */
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/* History:
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* Version 1.2
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* DMAx_Channel variable is checked for initialized channels in DMA_ChannelUninitialize function
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* Version 1.1
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* DMA2 peripheral added to build when HD, XL, HD_VL or CL device is used
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* Version 1.0
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* Initial release
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*/
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#include "DMA_STM32F10x.h"
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#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || \
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defined(STM32F10X_HD_VL) || defined(STM32F10X_CL)
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/* DMA2 peripheral exists on HD, XL, HD_VL and CL devices */
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#define STM32F10X_ENABLE_DMA2
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#endif
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/// DMA Variables
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static uint8_t DMA1_Channel; // Used DMA1 Channels
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#if defined (STM32F10X_ENABLE_DMA2)
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static uint8_t DMA2_Channel; // Used DMA2 Channels
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#endif
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/// DMA Functions
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/**
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\fn void DMA_ChannelInitialize (uint32_t dma, uint32_t channel)
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\brief Initialize DMA Channel
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\param[in] dma DMA number
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\param[in] channel DMA channel number
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*/
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void DMA_ChannelInitialize (uint32_t dma, uint32_t channel) {
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switch (dma) {
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case 1:
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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switch (channel) {
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case 1:
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DMA1_Channel1->CCR = 0;
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DMA1->IFCR = DMA_IFCR_CGIF1 | DMA_IFCR_CTEIF1 |
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DMA_IFCR_CHTIF1 | DMA_IFCR_CTCIF1;
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NVIC_ClearPendingIRQ(DMA1_Channel1_IRQn);
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NVIC_EnableIRQ(DMA1_Channel1_IRQn);
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break;
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case 2:
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DMA1_Channel2->CCR = 0;
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DMA1->IFCR = DMA_IFCR_CGIF2 | DMA_IFCR_CTEIF2 |
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DMA_IFCR_CHTIF2 | DMA_IFCR_CTCIF2;
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NVIC_ClearPendingIRQ(DMA1_Channel2_IRQn);
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NVIC_EnableIRQ(DMA1_Channel2_IRQn);
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break;
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case 3:
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DMA1_Channel3->CCR = 0;
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DMA1->IFCR = DMA_IFCR_CGIF3 | DMA_IFCR_CTEIF3 |
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DMA_IFCR_CHTIF3 | DMA_IFCR_CTCIF3;
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NVIC_ClearPendingIRQ(DMA1_Channel3_IRQn);
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NVIC_EnableIRQ(DMA1_Channel3_IRQn);
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break;
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case 4:
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DMA1_Channel4->CCR = 0;
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DMA1->IFCR = DMA_IFCR_CGIF4 | DMA_IFCR_CTEIF4 |
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DMA_IFCR_CHTIF4 | DMA_IFCR_CTCIF4;
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NVIC_ClearPendingIRQ(DMA1_Channel4_IRQn);
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NVIC_EnableIRQ(DMA1_Channel4_IRQn);
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break;
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case 5:
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DMA1_Channel5->CCR = 0;
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DMA1->IFCR = DMA_IFCR_CGIF5 | DMA_IFCR_CTEIF5 |
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DMA_IFCR_CHTIF5 | DMA_IFCR_CTCIF5;
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NVIC_ClearPendingIRQ(DMA1_Channel5_IRQn);
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NVIC_EnableIRQ(DMA1_Channel5_IRQn);
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break;
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case 6:
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DMA1_Channel6->CCR = 0;
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DMA1->IFCR = DMA_IFCR_CGIF6 | DMA_IFCR_CTEIF6 |
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DMA_IFCR_CHTIF6 | DMA_IFCR_CTCIF6;
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NVIC_ClearPendingIRQ(DMA1_Channel6_IRQn);
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NVIC_EnableIRQ(DMA1_Channel6_IRQn);
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break;
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case 7:
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DMA1_Channel7->CCR = 0;
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DMA1->IFCR = DMA_IFCR_CGIF7 | DMA_IFCR_CTEIF7 |
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DMA_IFCR_CHTIF7 | DMA_IFCR_CTCIF7;
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NVIC_ClearPendingIRQ(DMA1_Channel7_IRQn);
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NVIC_EnableIRQ(DMA1_Channel7_IRQn);
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break;
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}
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DMA1_Channel |= 1 << channel;
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break;
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#if defined (STM32F10X_ENABLE_DMA2)
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case 2:
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RCC->AHBENR |= RCC_AHBENR_DMA2EN;
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switch (channel) {
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case 1:
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DMA2_Channel1->CCR = 0;
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DMA2->IFCR = DMA_IFCR_CGIF1 | DMA_IFCR_CTEIF1 |
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DMA_IFCR_CHTIF1 | DMA_IFCR_CTCIF1;
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NVIC_ClearPendingIRQ(DMA2_Channel1_IRQn);
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NVIC_EnableIRQ(DMA2_Channel1_IRQn);
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break;
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case 2:
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DMA2_Channel2->CCR = 0;
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DMA2->IFCR = DMA_IFCR_CGIF2 | DMA_IFCR_CTEIF2 |
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DMA_IFCR_CHTIF2 | DMA_IFCR_CTCIF2;
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NVIC_ClearPendingIRQ(DMA2_Channel2_IRQn);
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NVIC_EnableIRQ(DMA2_Channel2_IRQn);
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break;
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case 3:
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DMA2_Channel3->CCR = 0;
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DMA2->IFCR = DMA_IFCR_CGIF3 | DMA_IFCR_CTEIF3 |
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DMA_IFCR_CHTIF3 | DMA_IFCR_CTCIF3;
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NVIC_ClearPendingIRQ(DMA2_Channel3_IRQn);
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NVIC_EnableIRQ(DMA2_Channel3_IRQn);
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break;
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case 4:
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DMA2_Channel4->CCR = 0;
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DMA2->IFCR = DMA_IFCR_CGIF4 | DMA_IFCR_CTEIF4 |
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DMA_IFCR_CHTIF4 | DMA_IFCR_CTCIF4;
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#if defined (STM32F10X_CL)
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NVIC_ClearPendingIRQ(DMA2_Channel4_IRQn);
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NVIC_EnableIRQ(DMA2_Channel4_IRQn);
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#else
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NVIC_ClearPendingIRQ(DMA2_Channel4_5_IRQn);
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NVIC_EnableIRQ(DMA2_Channel4_5_IRQn);
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#endif
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break;
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case 5:
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DMA2_Channel5->CCR = 0;
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DMA2->IFCR = DMA_IFCR_CGIF5 | DMA_IFCR_CTEIF5 |
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DMA_IFCR_CHTIF5 | DMA_IFCR_CTCIF5;
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#if defined (STM32F10X_CL)
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NVIC_ClearPendingIRQ(DMA2_Channel5_IRQn);
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NVIC_EnableIRQ(DMA2_Channel5_IRQn);
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#elif defined (STM32F10X_HD_VL)
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if (AFIO->MAPR2 & AFIO_MAPR2_MISC_REMAP) {
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/* DMA2 Channel 5 mapped at position 60 */
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NVIC_ClearPendingIRQ(DMA2_Channel5_IRQn);
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NVIC_EnableIRQ(DMA2_Channel5_IRQn);
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}
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else {
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NVIC_ClearPendingIRQ(DMA2_Channel4_5_IRQn);
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NVIC_EnableIRQ(DMA2_Channel4_5_IRQn);
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}
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#else
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NVIC_ClearPendingIRQ(DMA2_Channel4_5_IRQn);
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NVIC_EnableIRQ(DMA2_Channel4_5_IRQn);
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#endif
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break;
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}
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DMA2_Channel |= 1 << channel;
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break;
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#endif
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}
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}
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/**
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\fn void DMA_ChannelUninitialize (uint32_t dma, uint32_t channel)
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\brief Uninitialize DMA Channel
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\param[in] dma DMA number
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\param[in] channel DMA channel number
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*/
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void DMA_ChannelUninitialize (uint32_t dma, uint32_t channel) {
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switch (dma) {
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case 1:
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if (DMA1_Channel == 0) {
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// All DMA1 Channels are uninitialized
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return;
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}
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switch (channel) {
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case 1:
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NVIC_DisableIRQ(DMA1_Channel1_IRQn);
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DMA1_Channel1->CCR = 0;
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break;
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case 2:
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NVIC_DisableIRQ(DMA1_Channel2_IRQn);
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DMA1_Channel2->CCR = 0;
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break;
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case 3:
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NVIC_DisableIRQ(DMA1_Channel3_IRQn);
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DMA1_Channel3->CCR = 0;
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break;
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case 4:
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NVIC_DisableIRQ(DMA1_Channel4_IRQn);
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DMA1_Channel4->CCR = 0;
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break;
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case 5:
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NVIC_DisableIRQ(DMA1_Channel5_IRQn);
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DMA1_Channel5->CCR = 0;
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break;
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case 6:
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NVIC_DisableIRQ(DMA1_Channel6_IRQn);
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DMA1_Channel6->CCR = 0;
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break;
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case 7:
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NVIC_DisableIRQ(DMA1_Channel7_IRQn);
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DMA1_Channel7->CCR = 0;
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break;
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}
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DMA1_Channel &= ~(1 << channel);
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if (DMA1_Channel == 0){
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RCC->AHBENR &= ~RCC_AHBENR_DMA1EN;
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}
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break;
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#if defined (STM32F10X_ENABLE_DMA2)
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case 2:
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if (DMA2_Channel == 0) {
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// All DMA2 Channels are uninitialized
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return;
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}
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switch (channel) {
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case 1:
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NVIC_DisableIRQ(DMA2_Channel1_IRQn);
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DMA2_Channel1->CCR = 0;
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break;
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case 2:
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NVIC_DisableIRQ(DMA2_Channel2_IRQn);
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DMA2_Channel2->CCR = 0;
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break;
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case 3:
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NVIC_DisableIRQ(DMA2_Channel3_IRQn);
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DMA2_Channel3->CCR = 0;
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break;
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case 4:
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#if defined (STM32F10X_CL)
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NVIC_DisableIRQ(DMA2_Channel4_IRQn);
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#else
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/* If Channel 5 disabled, disable also Channel 4 */
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if (!(DMA2_Channel & (1 << 5))) {
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NVIC_DisableIRQ(DMA2_Channel4_5_IRQn);
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}
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#endif
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DMA2_Channel4->CCR = 0;
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break;
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case 5:
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#if defined (STM32F10X_CL)
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NVIC_DisableIRQ(DMA2_Channel5_IRQn);
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#elif defined (STM32F10X_HD_VL)
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if (AFIO->MAPR2 & AFIO_MAPR2_MISC_REMAP) {
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/* DMA2 Channel 5 mapped at position 60 */
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NVIC_DisableIRQ(DMA2_Channel5_IRQn);
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}
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else {
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/* If Channel 4 disabled, disable also Channel 5 */
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if (!(DMA2_Channel & (1 << 4))) {
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NVIC_DisableIRQ(DMA2_Channel4_5_IRQn);
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}
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}
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#else
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/* If Channel 4 disabled, disable also Channel 5 */
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if (!(DMA2_Channel & (1 << 4))) {
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NVIC_DisableIRQ(DMA2_Channel4_5_IRQn);
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}
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#endif
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DMA2_Channel5->CCR = 0;
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break;
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}
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DMA2_Channel &= ~(1 << channel);
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if (DMA2_Channel == 0){
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RCC->AHBENR &= ~RCC_AHBENR_DMA2EN;
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}
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break;
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#endif
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}
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}
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/// DMA1 Channel Events
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__weak void DMA1_Channel1_Event (uint32_t event) {;}
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__weak void DMA1_Channel2_Event (uint32_t event) {;}
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__weak void DMA1_Channel3_Event (uint32_t event) {;}
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__weak void DMA1_Channel4_Event (uint32_t event) {;}
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__weak void DMA1_Channel5_Event (uint32_t event) {;}
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__weak void DMA1_Channel6_Event (uint32_t event) {;}
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__weak void DMA1_Channel7_Event (uint32_t event) {;}
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#if defined (STM32F10X_ENABLE_DMA2)
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/// DMA2 Channel Events
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__weak void DMA2_Channel1_Event (uint32_t event) {;}
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__weak void DMA2_Channel2_Event (uint32_t event) {;}
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__weak void DMA2_Channel3_Event (uint32_t event) {;}
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__weak void DMA2_Channel4_Event (uint32_t event) {;}
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__weak void DMA2_Channel5_Event (uint32_t event) {;}
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#endif
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/**
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\fn void DMA1_Channel1_IRQHandler (void)
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\brief DMA1 Channel0 interrupt handler
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*/
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void DMA1_Channel1_IRQHandler (void) {
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uint32_t events;
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events = (DMA1->ISR >> 0) & DMA_CHANNEL_FLAGS;
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DMA1->IFCR = events << 0;
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DMA1_Channel1_Event(events);
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}
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/**
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\fn void DMA1_Channel2_IRQHandler (void)
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\brief DMA1 Channel2 interrupt handler
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*/
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void DMA1_Channel2_IRQHandler (void) {
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uint32_t events;
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events = (DMA1->ISR >> 4) & DMA_CHANNEL_FLAGS;
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DMA1->IFCR = events << 4;
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DMA1_Channel2_Event(events);
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}
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/**
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\fn void DMA1_Channel3_IRQHandler (void)
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\brief DMA1 Channel3 interrupt handler
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*/
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void DMA1_Channel3_IRQHandler (void) {
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uint32_t events;
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events = (DMA1->ISR >> 8) & DMA_CHANNEL_FLAGS;
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DMA1->IFCR = events << 8;
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DMA1_Channel3_Event(events);
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}
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/**
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\fn void DMA1_Channel4_IRQHandler (void)
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\brief DMA1 Channel4 interrupt handler
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*/
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void DMA1_Channel4_IRQHandler (void) {
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uint32_t events;
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events = (DMA1->ISR >> 12) & DMA_CHANNEL_FLAGS;
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DMA1->IFCR = events << 12;
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DMA1_Channel4_Event(events);
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}
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/**
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\fn void DMA1_Channel5_IRQHandler (void)
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\brief DMA1 Channel5 interrupt handler
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*/
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void DMA1_Channel5_IRQHandler (void) {
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uint32_t events;
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events = (DMA1->ISR >> 16) & DMA_CHANNEL_FLAGS;
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DMA1->IFCR = events << 16;
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DMA1_Channel5_Event(events);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\fn void DMA1_Channel6_IRQHandler (void)
|
||
|
|
\brief DMA1 Channel6 interrupt handler
|
||
|
|
*/
|
||
|
|
void DMA1_Channel6_IRQHandler (void) {
|
||
|
|
uint32_t events;
|
||
|
|
|
||
|
|
events = (DMA1->ISR >> 20) & DMA_CHANNEL_FLAGS;
|
||
|
|
DMA1->IFCR = events << 20;
|
||
|
|
DMA1_Channel6_Event(events);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\fn void DMA1_Channel7_IRQHandler (void)
|
||
|
|
\brief DMA1 Channel7 interrupt handler
|
||
|
|
*/
|
||
|
|
void DMA1_Channel7_IRQHandler (void) {
|
||
|
|
uint32_t events;
|
||
|
|
|
||
|
|
events = (DMA1->ISR >> 24) & DMA_CHANNEL_FLAGS;
|
||
|
|
DMA1->IFCR = events << 24;
|
||
|
|
DMA1_Channel7_Event(events);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
#if defined (STM32F10X_ENABLE_DMA2)
|
||
|
|
/**
|
||
|
|
\fn void DMA2_Channel1_IRQHandler (void)
|
||
|
|
\brief DMA2 Channel1 interrupt handler
|
||
|
|
*/
|
||
|
|
void DMA2_Channel1_IRQHandler (void) {
|
||
|
|
uint32_t events;
|
||
|
|
|
||
|
|
events = (DMA2->ISR >> 0) & DMA_CHANNEL_FLAGS;
|
||
|
|
DMA2->IFCR = events << 0;
|
||
|
|
DMA2_Channel1_Event(events);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\fn void DMA2_Channel2_IRQHandler (void)
|
||
|
|
\brief DMA2 Channel2 interrupt handler
|
||
|
|
*/
|
||
|
|
void DMA2_Channel2_IRQHandler (void) {
|
||
|
|
uint32_t events;
|
||
|
|
|
||
|
|
events = (DMA2->ISR >> 4) & DMA_CHANNEL_FLAGS;
|
||
|
|
DMA2->IFCR = events << 4;
|
||
|
|
DMA2_Channel2_Event(events);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\fn void DMA2_Channel3_IRQHandler (void)
|
||
|
|
\brief DMA2 Channel3 interrupt handler
|
||
|
|
*/
|
||
|
|
void DMA2_Channel3_IRQHandler (void) {
|
||
|
|
uint32_t events;
|
||
|
|
|
||
|
|
events = (DMA2->ISR >> 8) & DMA_CHANNEL_FLAGS;
|
||
|
|
DMA2->IFCR = events << 8;
|
||
|
|
DMA2_Channel3_Event(events);
|
||
|
|
}
|
||
|
|
|
||
|
|
#if !defined(STM32F10X_CL)
|
||
|
|
/**
|
||
|
|
\fn void DMA2_Channel4_IRQHandler (void)
|
||
|
|
\brief DMA2 Channel4 interrupt handler
|
||
|
|
*/
|
||
|
|
void DMA2_Channel4_IRQHandler (void) {
|
||
|
|
uint32_t events;
|
||
|
|
|
||
|
|
events = (DMA2->ISR >> 12) & DMA_CHANNEL_FLAGS;
|
||
|
|
DMA2->IFCR = events << 12;
|
||
|
|
DMA2_Channel4_Event(events);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(STM32F10X_HD_VL) || defined (STM32F10X_CL)
|
||
|
|
/**
|
||
|
|
\fn void DMA2_Channel5_IRQHandler (void)
|
||
|
|
\brief DMA2 Channel5 interrupt handler
|
||
|
|
*/
|
||
|
|
void DMA2_Channel5_IRQHandler (void) {
|
||
|
|
uint32_t events;
|
||
|
|
|
||
|
|
events = (DMA2->ISR >> 16) & DMA_CHANNEL_FLAGS;
|
||
|
|
DMA2->IFCR = events << 16;
|
||
|
|
DMA2_Channel5_Event(events);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/**
|
||
|
|
\fn void DMA2_Channel4_5_IRQHandler (void)
|
||
|
|
\brief DMA2 Channel 4 and 5 interrupt handler
|
||
|
|
*/
|
||
|
|
void DMA2_Channel4_5_IRQHandler (void) {
|
||
|
|
uint32_t events;
|
||
|
|
|
||
|
|
events = (DMA2->ISR >> 12) & DMA_CHANNEL_FLAGS;
|
||
|
|
if (events) {
|
||
|
|
/* Channel 4 events */
|
||
|
|
DMA2->IFCR = events << 12;
|
||
|
|
DMA2_Channel4_Event(events);
|
||
|
|
}
|
||
|
|
|
||
|
|
events = (DMA2->ISR >> 16) & DMA_CHANNEL_FLAGS;
|
||
|
|
if (events) {
|
||
|
|
/* Channel 5 events */
|
||
|
|
DMA2->IFCR = events << 16;
|
||
|
|
DMA2_Channel5_Event(events);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif
|