178 lines
6.7 KiB
C
178 lines
6.7 KiB
C
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/* -----------------------------------------------------------------------------
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* Copyright (c) 2013-2015 ARM Ltd.
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*
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* This software is provided 'as-is', without any express or implied warranty.
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* In no event will the authors be held liable for any damages arising from
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* the use of this software. Permission is granted to anyone to use this
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* software for any purpose, including commercial applications, and to alter
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* it and redistribute it freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software in
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* a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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*
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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*
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*
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* $Date: 22. September 2015
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* $Revision: V2.0
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*
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* Project: MCI Driver Definitions for STMicroelectronics STM32F10x
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* -------------------------------------------------------------------------- */
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#ifndef __MCI_STM32F10X_H
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#define __MCI_STM32F10X_H
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#include "stm32f10x.h"
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#include "GPIO_STM32F10x.h"
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#include "DMA_STM32F10x.h"
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#include "Driver_MCI.h"
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#include "RTE_Components.h"
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#include "RTE_Device.h"
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#include <string.h>
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#if (defined(RTE_Drivers_MCI0) && (RTE_SDIO == 0))
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#error "SDIO not configured in RTE_Device.h!"
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#endif
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/* SDIO DMA */
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#define SDIO_DMA_Instance DMAx_CHANNELy(RTE_SDIO_DMA_NUMBER, RTE_SDIO_DMA_CHANNEL)
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#define SDIO_DMA_Number RTE_SDIO_DMA_NUMBER
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#define SDIO_DMA_Channel RTE_SDIO_DMA_CHANNEL
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#define SDIO_DMA_Priority RTE_SDIO_DMA_PRIORITY
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#define SDIO_DMA_Handler DMAx_CHANNELy_EVENT(RTE_SDIO_DMA_NUMBER, RTE_SDIO_DMA_CHANNEL)
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#if (RTE_SDIO_BUS_WIDTH_4)
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#define SDIO_D0_Pin 1
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#define SDIO_D1_Pin 1
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#define SDIO_D2_Pin 1
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#define SDIO_D3_Pin 1
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#endif
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#if (RTE_SDIO_BUS_WIDTH_8)
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#define SDIO_D4_Pin 1
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#define SDIO_D5_Pin 1
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#define SDIO_D6_Pin 1
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#define SDIO_D7_Pin 1
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#endif
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#if (RTE_SDIO_CD_EN)
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#define MemoryCard_CD_Pin 1
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#define MemoryCard_CD_GPIOx RTE_SDIO_CD_PORT
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#define MemoryCard_CD_GPIO_Pin RTE_SDIO_CD_PIN
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#define MemoryCard_CD_GPIO_PuPd ((RTE_SDIO_CD_ACTIVE == 0) ? GPIO_IN_PULL_UP : GPIO_IN_PULL_DOWN)
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#define MemoryCard_CD_Pin_Active ((RTE_SDIO_CD_ACTIVE == 0) ? 0 : 1)
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#endif
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#if (RTE_SDIO_WP_EN)
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#define MemoryCard_WP_Pin 1
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#define MemoryCard_WP_GPIOx RTE_SDIO_WP_PORT
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#define MemoryCard_WP_GPIO_Pin RTE_SDIO_WP_PIN
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#define MemoryCard_WP_GPIO_PuPd ((RTE_SDIO_WP_ACTIVE == 0) ? GPIO_IN_PULL_UP : GPIO_IN_PULL_DOWN)
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#define MemoryCard_WP_Pin_Active ((RTE_SDIO_WP_ACTIVE == 0) ? 0 : 1)
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#endif
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/* Define 4-bit data bus width */
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#if defined(SDIO_D0_Pin) && defined(SDIO_D1_Pin) && defined(SDIO_D2_Pin) && defined(SDIO_D3_Pin)
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#define MCI_BUS_WIDTH_4 1U
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#else
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#define MCI_BUS_WIDTH_4 0U
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#endif
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/* Define 8-bit data bus width */
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#if defined(SDIO_D0_Pin) && defined(SDIO_D1_Pin) && defined(SDIO_D2_Pin) && defined(SDIO_D3_Pin) && \
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defined(SDIO_D4_Pin) && defined(SDIO_D5_Pin) && defined(SDIO_D6_Pin) && defined(SDIO_D7_Pin)
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#define MCI_BUS_WIDTH_8 1U
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#else
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#define MCI_BUS_WIDTH_8 0U
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#endif
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/* Define Card Detect pin existence */
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#if defined(MemoryCard_CD_Pin)
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#define MCI_CD_PIN 1U
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#else
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#define MCI_CD_PIN 0U
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#endif
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/* Define Write Protect pin existence */
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#if defined(MemoryCard_WP_Pin)
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#define MCI_WP_PIN 1U
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#else
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#define MCI_WP_PIN 0U
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#endif
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/* SDIO Adapter Clock definition */
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#define SDIOCLK (uint32_t)RTE_HCLK /* SDIO adapter clock */
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#ifndef SDIO_MASK_STBITERRIE
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#define SDIO_MASK_STBITERRIE 0U
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#endif
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#ifndef SDIO_STA_STBITERR
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#define SDIO_STA_STBITERR 0U
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#endif
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#ifndef SDIO_ICR_STBITERRC
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#define SDIO_ICR_STBITERRC 0U
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#endif
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/* Interrupt clear Mask */
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#define SDIO_ICR_BIT_Msk (SDIO_ICR_CCRCFAILC | \
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SDIO_ICR_DCRCFAILC | \
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SDIO_ICR_CTIMEOUTC | \
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SDIO_ICR_DTIMEOUTC | \
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SDIO_ICR_TXUNDERRC | \
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SDIO_ICR_RXOVERRC | \
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SDIO_ICR_CMDRENDC | \
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SDIO_ICR_CMDSENTC | \
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SDIO_ICR_DATAENDC | \
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SDIO_ICR_STBITERRC | \
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SDIO_ICR_DBCKENDC | \
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SDIO_ICR_SDIOITC)
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/* Error interrupt mask */
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#define SDIO_STA_ERR_BIT_Msk (SDIO_STA_CCRCFAIL | \
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SDIO_STA_DCRCFAIL | \
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SDIO_STA_CTIMEOUT | \
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SDIO_STA_DTIMEOUT | \
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SDIO_STA_STBITERR)
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/* Driver flag definitions */
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#define MCI_INIT ((uint8_t)0x01) /* MCI initialized */
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#define MCI_POWER ((uint8_t)0x02) /* MCI powered on */
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#define MCI_SETUP ((uint8_t)0x04) /* MCI configured */
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#define MCI_RESP_LONG ((uint8_t)0x08) /* Long response expected */
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#define MCI_RESP_CRC ((uint8_t)0x10) /* Check response CRC error */
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#define MCI_DATA_XFER ((uint8_t)0x20) /* Transfer data */
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#define MCI_DATA_READ ((uint8_t)0x40) /* Read transfer */
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#define MCI_READ_WAIT ((uint8_t)0x80) /* Read wait operation start */
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#define MCI_RESPONSE_EXPECTED_Msk (ARM_MCI_RESPONSE_SHORT | \
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ARM_MCI_RESPONSE_SHORT_BUSY | \
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ARM_MCI_RESPONSE_LONG)
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/* MCI Transfer Information Definition */
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typedef struct _MCI_XFER {
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uint8_t *buf; /* Data buffer */
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uint32_t cnt; /* Data bytes to transfer */
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} MCI_XFER;
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/* MCI Driver State Definition */
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typedef struct _MCI_INFO {
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ARM_MCI_SignalEvent_t cb_event; /* Driver event callback function */
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ARM_MCI_STATUS status; /* Driver status */
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uint32_t *response; /* Pointer to response buffer */
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MCI_XFER xfer; /* Data transfer description */
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uint8_t volatile flags; /* Driver state flags */
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uint32_t dctrl; /* Data control register value */
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uint32_t dlen; /* Data length register value */
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} MCI_INFO;
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#endif /* __MCI_STM32F10X_H */
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