232 lines
9.5 KiB
C
232 lines
9.5 KiB
C
/* -----------------------------------------------------------------------------
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* Copyright (c) 2013-2018 Arm Limited
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*
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* This software is provided 'as-is', without any express or implied warranty.
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* In no event will the authors be held liable for any damages arising from
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* the use of this software. Permission is granted to anyone to use this
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* software for any purpose, including commercial applications, and to alter
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* it and redistribute it freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software in
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* a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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*
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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*
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*
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* $Date: 4. October 2018
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* $Revision: V2.1
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*
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* Project: Ethernet Media Access (MAC) Definitions for STM32F10x
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* -------------------------------------------------------------------------- */
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#ifndef __EMAC_STM32F10X_H
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#define __EMAC_STM32F10X_H
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#include <string.h>
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#include "Driver_ETH_MAC.h"
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#include "stm32f10x.h"
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#include "RTE_Components.h"
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#include "RTE_Device.h"
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#if (defined(RTE_Drivers_ETH_MAC0) && !RTE_ETH)
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#error "Ethernet not configured in RTE_Device.h!"
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#endif
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#if (RTE_ETH_MII && RTE_ETH_RMII)
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#error "Ethernet interface configuration in RTE_Device.h is invalid!"
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#endif
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/* MDC management clock prescaler */
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#if (RTE_HCLK >= 60000000)
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#define MACMIIAR_CR_Val ETH_MACMIIAR_CR_Div42
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#elif (RTE_HCLK >= 35000000)
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#define MACMIIAR_CR_Val ETH_MACMIIAR_CR_Div26
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#elif (RTE_HCLK >= 20000000)
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#define MACMIIAR_CR_Val ETH_MACMIIAR_CR_Div16
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#error "HCLK too slow for Ethernet! Check settings in RTE_Device.h!"
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#endif
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#define ETH_MDC_GPIOx RTE_ETH_MDI_MDC_PORT
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#define ETH_MDC_GPIO_Pin RTE_ETH_MDI_MDC_PIN
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#define ETH_MDIO_GPIOx RTE_ETH_MDI_MDIO_PORT
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#define ETH_MDIO_GPIO_Pin RTE_ETH_MDI_MDIO_PIN
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#if (RTE_ETH_MII)
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#define ETH_MII 1
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#define ETH_TXD0_GPIOx RTE_ETH_MII_TXD0_PORT
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#define ETH_TXD0_GPIO_Pin RTE_ETH_MII_TXD0_PIN
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#define ETH_TXD1_GPIOx RTE_ETH_MII_TXD1_PORT
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#define ETH_TXD1_GPIO_Pin RTE_ETH_MII_TXD1_PIN
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#define ETH_TXD2_GPIOx RTE_ETH_MII_TXD2_PORT
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#define ETH_TXD2_GPIO_Pin RTE_ETH_MII_TXD2_PIN
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#define ETH_TXD3_GPIOx RTE_ETH_MII_TXD3_PORT
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#define ETH_TXD3_GPIO_Pin RTE_ETH_MII_TXD3_PIN
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#define ETH_RXD0_GPIOx RTE_ETH_MII_RXD0_PORT
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#define ETH_RXD0_GPIO_Pin RTE_ETH_MII_RXD0_PIN
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#define ETH_RXD1_GPIOx RTE_ETH_MII_RXD1_PORT
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#define ETH_RXD1_GPIO_Pin RTE_ETH_MII_RXD1_PIN
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#define ETH_RXD2_GPIOx RTE_ETH_MII_RXD2_PORT
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#define ETH_RXD2_GPIO_Pin RTE_ETH_MII_RXD2_PIN
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#define ETH_RXD3_GPIOx RTE_ETH_MII_RXD3_PORT
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#define ETH_RXD3_GPIO_Pin RTE_ETH_MII_RXD3_PIN
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#define ETH_TX_EN_GPIOx RTE_ETH_MII_TX_EN_PORT
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#define ETH_TX_EN_GPIO_Pin RTE_ETH_MII_TX_EN_PIN
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#define ETH_TX_CLK_GPIOx RTE_ETH_MII_TX_CLK_PORT
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#define ETH_TX_CLK_GPIO_Pin RTE_ETH_MII_TX_CLK_PIN
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#define ETH_RX_CLK_GPIOx RTE_ETH_MII_RX_CLK_PORT
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#define ETH_RX_CLK_GPIO_Pin RTE_ETH_MII_RX_CLK_PIN
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#define ETH_CRS_GPIOx RTE_ETH_MII_CRS_PORT
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#define ETH_CRS_GPIO_Pin RTE_ETH_MII_CRS_PIN
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#define ETH_COL_GPIOx RTE_ETH_MII_COL_PORT
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#define ETH_COL_GPIO_Pin RTE_ETH_MII_COL_PIN
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#define ETH_RX_DV_GPIOx RTE_ETH_MII_RX_DV_PORT
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#define ETH_RX_DV_GPIO_Pin RTE_ETH_MII_RX_DV_PIN
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#define ETH_RX_ER_GPIOx RTE_ETH_MII_RX_ER_PORT
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#define ETH_RX_ER_GPIO_Pin RTE_ETH_MII_RX_ER_PIN
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#else
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#define ETH_MII 0
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#define ETH_TXD0_GPIOx RTE_ETH_RMII_TXD0_PORT
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#define ETH_TXD0_GPIO_Pin RTE_ETH_RMII_TXD0_PIN
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#define ETH_TXD1_GPIOx RTE_ETH_RMII_TXD1_PORT
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#define ETH_TXD1_GPIO_Pin RTE_ETH_RMII_TXD1_PIN
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#define ETH_RXD0_GPIOx RTE_ETH_RMII_RXD0_PORT
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#define ETH_RXD0_GPIO_Pin RTE_ETH_RMII_RXD0_PIN
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#define ETH_RXD1_GPIOx RTE_ETH_RMII_RXD1_PORT
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#define ETH_RXD1_GPIO_Pin RTE_ETH_RMII_RXD1_PIN
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#define ETH_TX_EN_GPIOx RTE_ETH_RMII_TX_EN_PORT
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#define ETH_TX_EN_GPIO_Pin RTE_ETH_RMII_TX_EN_PIN
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#define ETH_REF_CLK_GPIOx RTE_ETH_RMII_REF_CLK_PORT
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#define ETH_REF_CLK_GPIO_Pin RTE_ETH_RMII_REF_CLK_PIN
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#define ETH_CRS_DV_GPIOx RTE_ETH_RMII_CRS_DV_PORT
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#define ETH_CRS_DV_GPIO_Pin RTE_ETH_RMII_CRS_DV_PIN
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#endif /* RTE_ETH_RMII */
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/* EMAC Driver state flags */
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#define EMAC_FLAG_INIT (1 << 0) // Driver initialized
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#define EMAC_FLAG_POWER (1 << 1) // Driver power on
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#define EMAC_FLAG_DMA_INIT (1 << 2) // DMA Initialized
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/* PTP subsecond increment value */
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#define PTPSSIR_Val(hclk) ((0x7FFFFFFFU + (hclk)/2U) / (hclk))
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/* TDES0 - DMA Descriptor TX Packet Control/Status */
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#define DMA_TX_OWN 0x80000000U // Own bit 1=DMA,0=CPU
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#define DMA_TX_IC 0x40000000U // Interrupt on completition
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#define DMA_TX_LS 0x20000000U // Last segment
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#define DMA_TX_FS 0x10000000U // First segment
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#define DMA_TX_DC 0x08000000U // Disable CRC
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#define DMA_TX_DP 0x04000000U // Disable pad
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#define DMA_TX_TTSE 0x02000000U // Transmit time stamp enable
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#define DMA_TX_CIC 0x00C00000U // Checksum insertion control
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#define DMA_TX_TER 0x00200000U // Transmit end of ring
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#define DMA_TX_TCH 0x00100000U // Second address chained
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#define DMA_TX_TTSS 0x00020000U // Transmit time stamp status
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#define DMA_TX_IHE 0x00010000U // IP header error status
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#define DMA_TX_ES 0x00008000U // Error summary
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#define DMA_TX_JT 0x00004000U // Jabber timeout
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#define DMA_TX_FF 0x00002000U // Frame flushed
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#define DMA_TX_IPE 0x00001000U // IP payload error
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#define DMA_TX_LC 0x00000800U // Loss of carrier
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#define DMA_TX_NC 0x00000400U // No carrier
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#define DMA_TX_LCOL 0x00000200U // Late collision
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#define DMA_TX_EC 0x00000100U // Excessive collision
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#define DMA_TX_VF 0x00000080U // VLAN frame
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#define DMA_TX_CC 0x00000078U // Collision count
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#define DMA_TX_ED 0x00000004U // Excessive deferral
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#define DMA_TX_UF 0x00000002U // Underflow error
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#define DMA_TX_DB 0x00000001U // Deferred bit
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/* TDES1 - DMA Descriptor TX Packet Control */
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#define DMA_RX_TBS2 0x1FFF0000U // Transmit buffer 2 size
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#define DMA_RX_TBS1 0x00001FFFU // Transmit buffer 1 size
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/* RDES0 - DMA Descriptor RX Packet Status */
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#define DMA_RX_OWN 0x80000000U // Own bit 1=DMA,0=CPU
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#define DMA_RX_AFM 0x40000000U // Destination address filter fail
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#define DMA_RX_FL 0x3FFF0000U // Frame length mask
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#define DMA_RX_ES 0x00008000U // Error summary
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#define DMA_RX_DE 0x00004000U // Descriptor error
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#define DMA_RX_SAF 0x00002000U // Source address filter fail
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#define DMA_RX_LE 0x00001000U // Length error
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#define DMA_RX_OE 0x00000800U // Overflow error
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#define DMA_RX_VLAN 0x00000400U // VLAN tag
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#define DMA_RX_FS 0x00000200U // First descriptor
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#define DMA_RX_LS 0x00000100U // Last descriptor
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#define DMA_RX_IPHCE 0x00000080U // IPv4 header checksum error
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#define DMA_RX_LC 0x00000040U // late collision
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#define DMA_RX_FT 0x00000020U // Frame type
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#define DMA_RX_RWT 0x00000010U // Receive watchdog timeout
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#define DMA_RX_RE 0x00000008U // Receive error
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#define DMA_RX_DRE 0x00000004U // Dribble bit error
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#define DMA_RX_CE 0x00000002U // CRC error
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#define DMA_RX_RMAM 0x00000001U // Rx MAC adr.match/payload cks.error
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/* RDES1 - DMA Descriptor RX Packet Control */
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#define DMA_RX_DIC 0x80000000U // Disable interrupt on completion
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#define DMA_RX_RBS2 0x1FFF0000U // Receive buffer 2 size
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#define DMA_RX_RER 0x00008000U // Receive end of ring
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#define DMA_RX_RCH 0x00004000U // Second address chained
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#define DMA_RX_RBS1 0x00001FFFU // Receive buffer 1 size
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/* EMAC DMA RX Descriptor */
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typedef struct rx_desc {
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uint32_t volatile Stat;
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uint32_t Ctrl;
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uint8_t const *Addr;
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struct rx_desc *Next;
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#if ((EMAC_CHECKSUM_OFFLOAD != 0) || (EMAC_TIME_STAMP != 0))
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uint32_t ExtStat;
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uint32_t Reserved[1];
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uint32_t TimeLo;
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uint32_t TimeHi;
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#endif
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} RX_Desc;
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/* EMAC DMA TX Descriptor */
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typedef struct tx_desc {
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uint32_t volatile CtrlStat;
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uint32_t Size;
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uint8_t *Addr;
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struct tx_desc *Next;
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#if ((EMAC_CHECKSUM_OFFLOAD != 0) || (EMAC_TIME_STAMP != 0))
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uint32_t Reserved[2];
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uint32_t TimeLo;
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uint32_t TimeHi;
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#endif
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} TX_Desc;
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/* EMAC Pin Descriptor */
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typedef struct _ETH_PIN {
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GPIO_TypeDef *port;
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uint16_t pin;
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} ETH_PIN;
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/* EMAC Driver Control Information */
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typedef struct {
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ARM_ETH_MAC_SignalEvent_t cb_event; // Event callback
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uint8_t flags; // Control and state flags
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uint8_t tx_index; // Transmit descriptor index
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uint8_t rx_index; // Receive descriptor index
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#if (EMAC_CHECKSUM_OFFLOAD)
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bool tx_cks_offload; // Checksum offload enabled/disabled
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#endif
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#if (EMAC_TIME_STAMP)
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uint8_t tx_ts_index; // Transmit Timestamp descriptor index
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#endif
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uint8_t *frame_end; // End of assembled frame fragments
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} EMAC_CTRL;
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#endif /* __EMAC_STM32F10X_H */
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