120 lines
4.9 KiB
C
120 lines
4.9 KiB
C
/* ----------------------------------------------------------------------
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* Copyright (C) 2013 ARM Limited. All rights reserved.
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*
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* $Date: 12. September 2013
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* $Revision: V1.00
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*
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* Project: USB Full/Low-Speed Driver Header for ST STM32F10x
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* -------------------------------------------------------------------- */
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#ifndef __USBREG_H
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#define __USBREG_H
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#define REG(x) (*((volatile unsigned int *)(x)))
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#define USB_BASE_ADDR 0x40005C00 /* USB Registers Base Address */
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#define USB_PMA_ADDR 0x40006000 /* USB Packet Memory Area Address */
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/* Common Registers */
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#define CNTR REG(USB_BASE_ADDR + 0x40) /* Control Register */
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#define ISTR REG(USB_BASE_ADDR + 0x44) /* Interrupt Status Register */
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#define FNR REG(USB_BASE_ADDR + 0x48) /* Frame Number Register */
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#define DADDR REG(USB_BASE_ADDR + 0x4C) /* Device Address Register */
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#define BTABLE REG(USB_BASE_ADDR + 0x50) /* Buffer Table Address Register */
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/* CNTR: Control Register Bit Definitions */
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#define CNTR_CTRM 0x8000 /* Correct Transfer Interrupt Mask */
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#define CNTR_PMAOVRM 0x4000 /* Packet Memory Aerea Over/underrun Interrupt Mask */
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#define CNTR_ERRM 0x2000 /* Error Interrupt Mask */
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#define CNTR_WKUPM 0x1000 /* Wake-up Interrupt Mask */
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#define CNTR_SUSPM 0x0800 /* Suspend Mode Interrupt Mask */
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#define CNTR_RESETM 0x0400 /* USB Reset Interrupt Mask */
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#define CNTR_SOFM 0x0200 /* Start of Frame Interrupt Mask */
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#define CNTR_ESOFM 0x0100 /* Expected Start of Frame Interrupt Mask */
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#define CNTR_RESUME 0x0010 /* Resume Request */
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#define CNTR_FSUSP 0x0008 /* Force Suspend */
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#define CNTR_LPMODE 0x0004 /* Low-power Mode */
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#define CNTR_PDWN 0x0002 /* Power Down */
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#define CNTR_FRES 0x0001 /* Force USB Reset */
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/* ISTR: Interrupt Status Register Bit Definitions */
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#define ISTR_CTR 0x8000 /* Correct Transfer */
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#define ISTR_PMAOVR 0x4000 /* Packet Memory Aerea Over/underrun */
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#define ISTR_ERR 0x2000 /* Error */
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#define ISTR_WKUP 0x1000 /* Wake-up */
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#define ISTR_SUSP 0x0800 /* Suspend Mode */
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#define ISTR_RESET 0x0400 /* USB Reset */
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#define ISTR_SOF 0x0200 /* Start of Frame */
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#define ISTR_ESOF 0x0100 /* Expected Start of Frame */
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#define ISTR_DIR 0x0010 /* Direction of Transaction */
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#define ISTR_EP_ID 0x000F /* EndPoint Identifier */
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/* FNR: Frame Number Register Bit Definitions */
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#define FNR_RXDP 0x8000 /* D+ Data Line Status */
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#define FNR_RXDM 0x4000 /* D- Data Line Status */
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#define FNR_LCK 0x2000 /* Locked */
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#define FNR_LSOF 0x1800 /* Lost SOF */
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#define FNR_FN 0x07FF /* Frame Number */
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/* DADDR: Device Address Register Bit Definitions */
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#define DADDR_EF 0x0080 /* Enable Function */
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#define DADDR_ADD 0x007F /* Device Address */
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/* EndPoint Registers */
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#define EPxREG(x) REG(USB_BASE_ADDR + 4*(x))
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/* EPxREG: EndPoint Registers Bit Definitions */
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#define EP_CTR_RX 0x8000 /* Correct RX Transfer */
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#define EP_DTOG_RX 0x4000 /* RX Data Toggle */
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#define EP_STAT_RX 0x3000 /* RX Status */
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#define EP_SETUP 0x0800 /* EndPoint Setup */
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#define EP_TYPE 0x0600 /* EndPoint Type */
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#define EP_KIND 0x0100 /* EndPoint Kind */
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#define EP_CTR_TX 0x0080 /* Correct TX Transfer */
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#define EP_DTOG_TX 0x0040 /* TX Data Toggle */
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#define EP_STAT_TX 0x0030 /* TX Status */
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#define EP_EA 0x000F /* EndPoint Address */
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/* EndPoint Register Mask (No Toggle Fields) */
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#define EP_MASK (EP_CTR_RX|EP_SETUP|EP_TYPE|EP_KIND|EP_CTR_TX|EP_EA)
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/* EP_TYPE: EndPoint Types */
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#define EP_BULK 0x0000 /* BULK EndPoint */
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#define EP_CONTROL 0x0200 /* CONTROL EndPoint */
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#define EP_ISOCHRONOUS 0x0400 /* ISOCHRONOUS EndPoint */
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#define EP_INTERRUPT 0x0600 /* INTERRUPT EndPoint */
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/* EP_KIND: EndPoint Kind */
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#define EP_DBL_BUF EP_KIND /* Double Buffer for Bulk Endpoint */
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#define EP_STATUS_OUT EP_KIND /* Status Out for Control Endpoint */
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/* EP_STAT_TX: TX Status */
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#define EP_TX_DIS 0x0000 /* Disabled */
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#define EP_TX_STALL 0x0010 /* Stalled */
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#define EP_TX_NAK 0x0020 /* NAKed */
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#define EP_TX_VALID 0x0030 /* Valid */
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/* EP_STAT_RX: RX Status */
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#define EP_RX_DIS 0x0000 /* Disabled */
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#define EP_RX_STALL 0x1000 /* Stalled */
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#define EP_RX_NAK 0x2000 /* NAKed */
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#define EP_RX_VALID 0x3000 /* Valid */
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/* Endpoint Buffer Descriptor */
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typedef struct _EP_BUF_DSCR {
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unsigned int ADDR_TX;
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unsigned int COUNT_TX;
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unsigned int ADDR_RX;
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unsigned int COUNT_RX;
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} EP_BUF_DSCR;
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#define EP_ADDR_MASK 0xFFFE /* Address Mask */
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#define EP_COUNT_MASK 0x03FF /* Count Mask */
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#endif /* __USBREG_H */
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